Cypress CY7C0430CV manual Document History, Issue Orig. Description of Change Date, Szv, Fsg, Ydt

Page 37

CY7C0430BV

CY7C0430CV

Document History Page

Document Title: CY7C0430BV, CY7C0430CV 10 Gb/s 3.3V QuadPort DSE Family

Document Number: 38-06027

REV.

ECN NO.

Issue

Orig. of

Description of Change

Date

Change

 

 

 

 

 

**

109906

09/10/01

SZV

Change from Spec number: 38-01052 to 38-06027

 

 

 

 

 

*A

115042

05/23/02

FSG

Remove Preliminary, TM from DSE

 

 

 

 

Change RUNBIST to CYBIST

 

 

 

 

Updated ISB values

 

 

 

 

Added notes 7 and 9

 

 

 

 

Increased commercial prime bin to 135 MHz

*B

464083

SEE ECN

YDT

Part numbers updated to reflect the recent die revisions

 

 

 

 

Removed 1/2M and 1/4M parts

 

 

 

 

Changed title of data sheet

Document #: 38-06027 Rev. *B

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Contents QuadPort DSE Family Applications FeaturesCypress Semiconductor Corporation Processor Pre-processed Data Path Functional DescriptionProcessor Processed Data Path Queue #1Port 1 Operation-control Logic Blocks2 Top Level Logic Block DiagramAddress Readback is independent of CEs Port 1 Operation-Control Logic Block DiagramBall Grid Array BGA Top View Pin ConfigurationPin Definitions Selection GuideCY7C0430CV Unit Port DescriptionCounter Interrupt Flag Output . Flag is asserted LOW Mask Register Readback Input . When asserted LOWMaximum Ratings Electrical Characteristics Over the Operating RangeOperating Range CapacitanceAC Test Load Three-State DelayNormal Load TAP LoadChip Enable Hold Time Chip Enable Set-up TimeOutput Enable to Data Valid Maximum FrequencyJtag Timing and Switching Waveforms Master Reset10 Switching WaveformsAddress CLKData OUT LatencyRead-to-Write-to-Read OE = Bank Select Read 17Address B1 Read No Operation WriteRead with Address Counter Advance23 Read-to-Write-to-Read OE Controlled19, 20, 21Cntld Cntinc DataoutAddress Internal Write with Address Counter Advance 24Write External Write with Counter HoldCounter Write Read Reset Address Counter Reset 21, 26Data Data OUT Address nCntrd Internal Load and Read Address Counter28Load Read Data with Counter External Address Internal Mkld Load and Read Mask RegisterMkrd Mask Internal Value Load Read Mask Register ValuePort 1 Write to Port 2 Read34, 35 Mailbox Interrupt Timing40, 41, 42, 43 Counter Interrupt 37, 38Operation Mode OperationInterrupts Master ResetInterrupt Operation Example Port FunctionCntrd Mkrd Address Counter Control OperationsCntinc = Cntld = Cntrst = CLK Counter-Mask Register Test Access Port TAP-Test Clock TCK Disabling the Jtag FeatureTest Mode Select Performing a TAP ResetIdentification ID Register Non-Debug Mode Go-NoGoTAP Instruction Set Mbist Control States Debug ModeBoundary Scan Cells BSC P4IO17-9EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram FSM53MUX JTAG/BIST TAP Controller Block DiagramMbist Debug Register MDR 391 Bist TAP ControllerInstruction Identification Codes Description Scan Registers Sizes Register Name Bit SizePlaces the bypass register BYR between TDI and TDO Between TDI and TDOMbist Control Register MCR MCR10 Mode CE0 Boundary Scan Order Cell # Signal Name Bump Ball IDCLKP4 CLKP3CLKP2 Ordering Information Lead Pbga 27 x 27 x 2.33 mm BG272 Package DiagramDocument History Issue Orig. Description of Change DateSZV FSG
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