Cypress CY7C0430BV Address Counter Control Operations, Cntrd Mkrd, Cntinc = Cntld = Cntrst = CLK

Page 24

CY7C0430BV

CY7C0430CV

Address Counter Control Operations

Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for the fast interleaved memory applications. A port’s burst counter is loaded with the port’s Counter Load pin (CNTLD). When the port’s Counter Increment (CNTINC) is asserted, the address counter will increment on each LOW to HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTINC is deasserted. Depending on the mask register state, the counter can address the entire memory array and will loop back to start. Counter Reset (CNTRST) is used to reset the Burst Counter (the Mask Register value is unaffected). When using the counter in readback mode, the internal address value of the counter will be read back on the address lines when Counter Readback Signal (CNTRD) is asserted.

Figure 1 provides a block diagram of the readback operation. Table 2 lists control signals required for counter operations. The signals are listed based on their priority. For example, Master Reset takes precedence over Counter Reset, and Counter Load has lower priority than Mask Register Load (described below). All counter operations are independent of Chip Enables (CE0 and CE1). When the address readback operation is performed the data I/Os are three-stated (if CEs are active) and one-clock cycle (no-operation cycle) latency is experienced. The address will be read at time tCA2 from the rising edge of the clock following the no-operation cycle. The read back address can be either of the burst counter or the mask register based on the levels of Counter Read signal (CNTRD) and Mask Register Read signal (MKRD). Both signals are synchronized to the port's clock as shown in Table 2. Counter read has a higher priority than mask read.

CNTRD

MKRD

MKLD = 1

Bidirectional

Address Lines

CNTINC = 1

CNTLD = 1

CNTRST = 1

CLK

Readback

Register

Mask

Register

Counter/

Address

Register

Addr.

Memory

Array

Figure 1. Counter and Mask Register Read Back on Address Lines

Document #: 38-06027 Rev. *B

Page 24 of 37

[+] Feedback

Page 23 Page 25
Image 24
Page 23 Page 25
Contents Features QuadPort DSE Family ApplicationsCypress Semiconductor Corporation Functional Description Processor Pre-processed Data PathProcessor Processed Data Path Queue #1Top Level Logic Block Diagram Port 1 Operation-control Logic Blocks2Port 1 Operation-Control Logic Block Diagram Address Readback is independent of CEsPin Configuration Ball Grid Array BGA Top ViewSelection Guide Pin DefinitionsCY7C0430CV Unit Port DescriptionMask Register Readback Input . When asserted LOW Counter Interrupt Flag Output . Flag is asserted LOWElectrical Characteristics Over the Operating Range Maximum RatingsOperating Range CapacitanceThree-State Delay AC Test LoadNormal Load TAP LoadChip Enable Set-up Time Chip Enable Hold TimeOutput Enable to Data Valid Maximum FrequencyJtag Timing and Switching Waveforms Switching Waveforms Master Reset10CLK AddressData OUT LatencyBank Select Read 17 Read-to-Write-to-Read OE =Address B1 Read No Operation WriteRead-to-Write-to-Read OE Controlled19, 20, 21 Read with Address Counter Advance23Cntld Cntinc DataoutWrite with Address Counter Advance 24 Address InternalWrite External Write with Counter HoldCounter Reset 21, 26 Counter Write Read Reset AddressData Data OUT Address nLoad and Read Address Counter28 Cntrd InternalLoad Read Data with Counter External Address Internal Load and Read Mask Register MkldMkrd Mask Internal Value Load Read Mask Register ValuePort 1 Write to Port 2 Read34, 35 Counter Interrupt 37, 38 Mailbox Interrupt Timing40, 41, 42, 43Mode Operation OperationMaster Reset InterruptsInterrupt Operation Example Port FunctionAddress Counter Control Operations Cntrd MkrdCntinc = Cntld = Cntrst = CLK Counter-Mask Register Disabling the Jtag Feature Test Access Port TAP-Test Clock TCKTest Mode Select Performing a TAP ResetNon-Debug Mode Go-NoGo Identification ID RegisterTAP Instruction Set Debug Mode Mbist Control StatesBoundary Scan Cells BSC P4IO17-9TAP Controller State Diagram FSM53 EXIT2-IR UPDATE-DR UPDATE-IRJTAG/BIST TAP Controller Block Diagram MUXMbist Debug Register MDR 391 Bist TAP ControllerScan Registers Sizes Register Name Bit Size Instruction Identification Codes DescriptionPlaces the bypass register BYR between TDI and TDO Between TDI and TDOMbist Control Register MCR MCR10 Mode Boundary Scan Order Cell # Signal Name Bump Ball ID CE0CLKP4 CLKP3CLKP2 Ordering Information Package Diagram Lead Pbga 27 x 27 x 2.33 mm BG272Issue Orig. Description of Change Date Document HistorySZV FSG
Top Page Image Contents