Cypress CY7C0430CV, CY7C0430BV manual Pin Configuration, Ball Grid Array BGA Top View

Page 5

CY7C0430BV

CY7C0430CV

Pin Configuration

272-ball Grid Array (BGA)

Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

Note:

LB

I/O17

I/O15

I/O13

I/O11

I/O9

I/O16

I/O14

I/O12

I/O10

I/O10

I/O12

I/O14

I/O16

I/O9

I/O11

I/O13

I/O15

I/O17

LB

P1

P2

P2

P2

P2

P2

P1

P1

P1

P1

P4

P4

P4

P4

P3

P3

P3

P3

P3

P4

VDD1

I/O16

I/O14

I/O12

I/O10

I/O17

I/O13

I/O11

TMS

TDI

I/O11

I/O13

I/O17

I/O10

I/O12

I/O14

I/O16

VDD1

UB

UB

P1

P2

P2

P2

P2

P1

P1

P1

P4

P4

P4

P3

P3

P3

P3

P4

A14

A15

CE1

I/O15

VSS2

VSS2

I/O9

TCK

TDO

I/O9

VSS2

VSS2

I/O15

CE1

A15

A14

CE0

R/W

R/W

CE0

P1

P1

P1

P1

P1

P1

P1

P4

P4

P4

P4

P4

P4

P4

VSS1

A12

A13

VDD2

VSS2

VSS2

VDD2

VDD

VSS

VSS

VDD

VDD2

VSS2

VSS2

VDD2

A13

A12

VSS1

OE

OE

P1

P1

P1

P4

P4

P4

A10

A11

A11

A10

MKRD

CNTRD

CNTRD

MKRD

P1

P1

P1

P1

P4

P4

P4

P4

A7

A8

A9

A9

A8

A7

CNTINT

CNTINT

P1

P1

P1

P1

P4

P4

P4

P4

VSS1

A5

A6

A6

A5

VSS1

CNTINC

CNTINC

P1

P1

P1

P4

P4

P4

A3

A4

A4

A3

MKLD

CNTLD

CNTLD

MKLD

P1

P1

P1

P1

P4

P4

P4

P4

VDD1

A1

A2

VDD

GND[4]

GND[4]

GND[4]

GND[4]

VDD

A2

A1

VDD1

P1

P1

P4

P4

A0

CLK

GND[4]

GND[4]

GND[4]

GND[4]

CLK

A0

INT

CNTRST

CNTRST

INT

P1

P1

P1

P1

P4

P4

P4

P4

A0

VSS

GND[4]

GND[4]

GND[4]

GND[4]

VSS

A0

INT

CNTRST

CNTRST

INT

P2

P2

P2

P3

P3

P3

VDD1

A1

A2

CLK

GND[4]

GND[4]

GND[4]

GND[4]

CLK

A2

A1

VDD1

P2

P2

P2

P3

P3

P3

A3

A4

A4

A3

MKLD

CNTLD

CNTLD

MKLD

P2

P2

P2

P2

P3

P3

P3

P3

VSS1

A5

A6

A6

A5

VSS1

CNTINC

CNTINC

P2

P2

P2

P3

P3

P3

A7

A8

A9

A9

A8

A7

CNTINT

CNTINT

P2

P2

P2

P2

P3

P3

P3

P3

A10

A11

A11

A10

MKRD

CNTRD

CNTRD

MKRD

P2

P2

P2

P2

P3

P3

P3

P3

VSS1

A12

A13

VDD2

VSS2

VSS2

VDD2

VDD

VSS

VSS

VDD

VDD2

VSS2

VSS2

VDD2

A13

A12

VSS1

OE

OE

P2

P2

P2

P3

P3

P3

A14

A15

CE1

I/O6

VSS2

VSS2

I/O0

NC

NC

I/O0

VSS2

VSS2

I/O6

CE1

A15

A14

CE0

R/W

R/W

CE0

P2

P2

P2

P2

P2

P2

P2

P3

P3

P3

P3

P3

P3

P3

VDD1

I/O7

I/O5

I/O3

I/O1

I/O8

I/O4

I/O2

CLKBIST

I/O2

I/O4

I/O8

I/O1

I/O3

I/O5

I/O7

VDD1

UB

MRST

UB

P2

P1

P1

P1

P1

P2

P2

P2

P3

P3

P3

P4

P4

P4

P4

P3

I/O8

I/O6

I/O4

I/O2

I/O0

1/O7

I/O5

I/O3

I/O1

I/O1

I/O3

I/O5

I/O7

I/O0

I/O2

I/O4

I/O6

I/O8

LB

LB

P2

P1

P1

P1

P1

P1

P2

P2

P2

P2

P3

P3

P3

P3

P4

P4

P4

P4

P4

P3

4. Central Leads are for thermal dissipation only. They are connected to device VSS.

Document #: 38-06027 Rev. *B

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Contents Cypress Semiconductor Corporation FeaturesQuadPort DSE Family Applications Processor Pre-processed Data Path Functional DescriptionProcessor Processed Data Path Queue #1Port 1 Operation-control Logic Blocks2 Top Level Logic Block DiagramAddress Readback is independent of CEs Port 1 Operation-Control Logic Block DiagramBall Grid Array BGA Top View Pin ConfigurationPin Definitions Selection GuideCY7C0430CV Unit Port DescriptionCounter Interrupt Flag Output . Flag is asserted LOW Mask Register Readback Input . When asserted LOWMaximum Ratings Electrical Characteristics Over the Operating RangeOperating Range CapacitanceAC Test Load Three-State DelayNormal Load TAP LoadChip Enable Hold Time Chip Enable Set-up TimeOutput Enable to Data Valid Maximum FrequencyJtag Timing and Switching Waveforms Master Reset10 Switching WaveformsAddress CLKData OUT LatencyRead-to-Write-to-Read OE = Bank Select Read 17Address B1 Read No Operation WriteRead with Address Counter Advance23 Read-to-Write-to-Read OE Controlled19, 20, 21Cntld Cntinc DataoutAddress Internal Write with Address Counter Advance 24Write External Write with Counter HoldCounter Write Read Reset Address Counter Reset 21, 26Data Data OUT Address nLoad Read Data with Counter External Address Internal Load and Read Address Counter28Cntrd Internal Mkld Load and Read Mask RegisterMkrd Mask Internal Value Load Read Mask Register ValuePort 1 Write to Port 2 Read34, 35 Mailbox Interrupt Timing40, 41, 42, 43 Counter Interrupt 37, 38Operation Mode OperationInterrupts Master ResetInterrupt Operation Example Port FunctionCntinc = Cntld = Cntrst = CLK Address Counter Control OperationsCntrd Mkrd Counter-Mask Register Test Access Port TAP-Test Clock TCK Disabling the Jtag FeatureTest Mode Select Performing a TAP ResetTAP Instruction Set Non-Debug Mode Go-NoGoIdentification ID Register Mbist Control States Debug ModeBoundary Scan Cells BSC P4IO17-9EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram FSM53MUX JTAG/BIST TAP Controller Block DiagramMbist Debug Register MDR 391 Bist TAP ControllerInstruction Identification Codes Description Scan Registers Sizes Register Name Bit SizePlaces the bypass register BYR between TDI and TDO Between TDI and TDOMbist Control Register MCR MCR10 Mode CE0 Boundary Scan Order Cell # Signal Name Bump Ball IDCLKP4 CLKP3CLKP2 Ordering Information Lead Pbga 27 x 27 x 2.33 mm BG272 Package DiagramDocument History Issue Orig. Description of Change DateSZV FSG