Cypress CY7C0430CV manual Read-to-Write-to-Read OE Controlled19, 20, 21, Cntld Cntinc, Dataout

Page 15

CY7C0430BV

CY7C0430CV

Switching Waveforms (continued)

Read-to-Write-to-Read (OE Controlled)[19, 20, 21, 22]

tCH2 tCYC2tCL2

CLK

CE

R/W

tSC tHC

tSW tHW

tSW tHW

ADDRESS

 

 

 

 

 

 

An

 

 

 

 

 

An+1

 

 

 

 

An+2

 

 

 

An+3

 

 

 

 

An+4

 

 

 

An+5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA

 

 

 

 

 

 

 

 

tHA

 

 

tSD

tHD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATAIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dn+2

 

 

 

 

Dn+3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCD2

 

 

 

 

 

 

 

 

 

 

 

 

 

tCD2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATAOUT

Q

n

Q

 

 

n+4

 

 

 

tCKLZ

tOHZ

 

OE

Read Write Read

Read with Address Counter Advance[23, 24]

 

tCYC2

 

 

 

 

 

tCH2

tCL2

 

 

 

 

CLK

 

 

 

 

 

 

tSA

tHA

 

 

 

 

 

ADDRESS

An

 

 

 

 

 

tSCLD

tHCLD

 

 

 

 

CNTLD

 

 

 

 

 

 

CNTINC

 

tSCINC

tHCINC

 

 

 

 

 

 

 

 

 

 

 

tCD2

 

 

 

 

DATAOUT

Qx–1

Qx

Qn

Qn+1

Qn+2

Qn+3

 

Read

tDC

 

Counter Hold

Read with Counter

 

External

Read with Counter

 

 

Address

 

 

 

 

 

Notes:

 

 

 

 

 

 

23. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = CNTRD = VIH.

 

 

24. The “Internal Address” is equal to the “External Address” when CNTLD = VIL.

 

 

 

Document #: 38-06027 Rev. *B

 

 

 

 

Page 15 of 37

[+] Feedback

Image 15
Contents Features QuadPort DSE Family ApplicationsCypress Semiconductor Corporation Queue #1 Functional DescriptionProcessor Pre-processed Data Path Processor Processed Data PathPort 1 Operation-control Logic Blocks2 Top Level Logic Block DiagramAddress Readback is independent of CEs Port 1 Operation-Control Logic Block DiagramBall Grid Array BGA Top View Pin ConfigurationPort Description Selection GuidePin Definitions CY7C0430CV UnitCounter Interrupt Flag Output . Flag is asserted LOW Mask Register Readback Input . When asserted LOWCapacitance Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeTAP Load Three-State DelayAC Test Load Normal LoadMaximum Frequency Chip Enable Set-up TimeChip Enable Hold Time Output Enable to Data ValidJtag Timing and Switching Waveforms Master Reset10 Switching WaveformsLatency CLKAddress Data OUTRead No Operation Write Bank Select Read 17Read-to-Write-to-Read OE = Address B1Dataout Read-to-Write-to-Read OE Controlled19, 20, 21Read with Address Counter Advance23 Cntld CntincCounter Hold Write with Address Counter Advance 24Address Internal Write External Write withAddress n Counter Reset 21, 26Counter Write Read Reset Address Data Data OUTLoad and Read Address Counter28 Cntrd InternalLoad Read Data with Counter External Address Internal Load Read Mask Register Value Load and Read Mask RegisterMkld Mkrd Mask Internal ValuePort 1 Write to Port 2 Read34, 35 Mailbox Interrupt Timing40, 41, 42, 43 Counter Interrupt 37, 38Operation Mode OperationPort Function Master ResetInterrupts Interrupt Operation ExampleAddress Counter Control Operations Cntrd MkrdCntinc = Cntld = Cntrst = CLK Counter-Mask Register Performing a TAP Reset Disabling the Jtag FeatureTest Access Port TAP-Test Clock TCK Test Mode SelectNon-Debug Mode Go-NoGo Identification ID RegisterTAP Instruction Set P4IO17-9 Debug ModeMbist Control States Boundary Scan Cells BSCEXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram FSM53Bist TAP Controller JTAG/BIST TAP Controller Block DiagramMUX Mbist Debug Register MDR 391Between TDI and TDO Scan Registers Sizes Register Name Bit SizeInstruction Identification Codes Description Places the bypass register BYR between TDI and TDOMbist Control Register MCR MCR10 Mode CLKP3 Boundary Scan Order Cell # Signal Name Bump Ball IDCE0 CLKP4CLKP2 Ordering Information Lead Pbga 27 x 27 x 2.33 mm BG272 Package DiagramFSG Issue Orig. Description of Change DateDocument History SZV