Cypress CY7C0430CV manual Boundary Scan Order Cell # Signal Name Bump Ball ID, CE0, CLKP4, CLKP3

Page 33

CY7C0430BV

CY7C0430CV

Table 9. Boundary Scan Order

Cell #

 

 

 

 

 

Signal Name

Bump (Ball) ID

 

 

 

 

2

 

A0_P4

K20

 

 

 

 

4

 

A1_P4

J19

 

 

 

 

6

 

A2_P4

J18

 

 

 

 

8

 

A3_P4

H20

 

 

 

 

10

 

A4_P4

H19

 

 

 

 

12

 

A5_P4

G19

 

 

 

 

14

 

A6_P4

G18

 

 

 

 

16

 

A7_P4

F20

 

 

 

 

18

 

A8_P4

F19

 

 

 

 

20

 

A9_P4

F18

 

 

 

 

22

 

A10_P4

E20

 

 

 

 

24

 

A11_P4

E19

 

 

 

 

26

 

A12_P4

D19

 

 

 

 

28

 

A13_P4

D18

 

 

 

 

30

 

A14_P4

C20

 

 

 

 

32

 

A15_P4

C19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

34

 

 

 

 

 

 

 

 

 

 

 

 

 

_P4

F17

CNTINT

36

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_P4

K18

CNTRST

38

 

 

 

 

 

 

 

 

 

_P4

H18

MKLD

40

 

 

 

 

 

 

 

 

 

 

 

_P4

H17

CNTLD

42

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_P4

G17

CNTINC

44

 

 

 

 

 

 

 

 

 

 

 

 

_P4

E17

CNTRD

46

 

 

 

 

 

 

 

 

 

 

_P4

E18

MKRD

48

 

 

 

_P4

A20

LB

50

 

 

 

 

_P4

B19

UB

52

 

 

 

 

 

_P4

D17

OE

54

 

 

 

 

 

 

 

_P4

C16

R/W

56

 

CE1_P4

C18

 

 

 

 

 

 

58

 

 

 

 

 

 

 

 

_P4

C17

CE0

60

 

 

 

 

 

 

_P4

K19

INT

62

 

CLK_P4

K17

 

 

 

 

64

 

A0_P3

L20

 

 

 

 

66

 

A1_P3

M19

 

 

 

 

68

 

A2_P3

M18

 

 

 

 

70

 

A3_P3

N20

 

 

 

 

72

 

A4_P3

N19

 

 

 

 

74

 

A5_P3

P19

 

 

 

 

76

 

A6_P3

P18

 

 

 

 

78

 

A7_P3

R20

 

 

 

 

80

 

A8_P3

R19

 

 

 

 

82

 

A9_P3

R18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 9. Boundary Scan Order (continued)

Cell #

 

 

 

 

 

Signal Name

Bump (Ball) ID

 

 

 

 

84

 

A10_P3

T20

 

 

 

 

86

 

A11_P3

T19

 

 

 

 

88

 

A12_P3

U19

 

 

 

 

90

 

A13_P3

U18

 

 

 

 

92

 

A14_P3

V20

 

 

 

 

94

 

A15_P3

V19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

96

 

 

 

 

 

 

 

 

 

 

 

 

 

_P3

R17

CNTINT

98

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_P3

L18

CNTRST

100

 

 

 

 

 

 

 

 

 

_P3

N18

MKLD

102

 

 

 

 

 

 

 

 

 

 

 

_P3

N17

CNTLD

104

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_P3

P17

CNTINC

106

 

 

 

 

 

 

 

 

 

 

 

 

_P3

T17

CNTRD

108

 

 

 

 

 

 

 

 

 

 

_P3

T18

MKRD

110

 

 

 

_P3

Y20

LB

112

 

 

 

 

_P3

W19

UB

114

 

 

 

 

 

_P3

U17

OE

116

 

 

 

 

 

 

 

_P3

V16

R/W

118

 

CE1_P3

V18

 

 

 

 

 

 

120

 

 

 

 

 

 

 

 

_P3

V17

CE0

122

 

 

 

 

 

 

_P3

L19

INT

124

 

CLK_P3

M17

 

 

 

 

126

 

IO0_P4

Y15

 

 

 

 

128

 

IO1_P4

W15

 

 

 

 

130

 

IO2_P4

Y16

 

 

 

 

132

 

IO3_P4

W16

 

 

 

 

134

 

IO4_P4

Y17

 

 

 

 

136

 

IO5_P4

W17

 

 

 

 

138

 

IO6_P4

Y18

 

 

 

 

140

 

IO7_P4

W18

 

 

 

 

142

 

IO8_P4

Y19

 

 

 

 

144

 

IO0_P3

V12

 

 

 

 

146

 

IO1_P3

Y11

 

 

 

 

148

 

IO2_P3

W12

 

 

 

 

150

 

IO3_P3

Y12

 

 

 

 

152

 

IO4_P3

W13

 

 

 

 

154

 

IO5_P3

Y13

 

 

 

 

156

 

IO6_P3

V15

 

 

 

 

158

 

IO7_P3

Y14

 

 

 

 

160

 

IO8_P3

W14

 

 

 

 

162

 

IO0_P1

Y6

 

 

 

 

164

 

IO1_P1

W6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-06027 Rev. *B

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Contents Features QuadPort DSE Family ApplicationsCypress Semiconductor Corporation Processor Pre-processed Data Path Functional DescriptionProcessor Processed Data Path Queue #1Port 1 Operation-control Logic Blocks2 Top Level Logic Block DiagramAddress Readback is independent of CEs Port 1 Operation-Control Logic Block DiagramBall Grid Array BGA Top View Pin ConfigurationPin Definitions Selection GuideCY7C0430CV Unit Port DescriptionCounter Interrupt Flag Output . Flag is asserted LOW Mask Register Readback Input . When asserted LOWMaximum Ratings Electrical Characteristics Over the Operating RangeOperating Range CapacitanceAC Test Load Three-State DelayNormal Load TAP LoadChip Enable Hold Time Chip Enable Set-up TimeOutput Enable to Data Valid Maximum FrequencyJtag Timing and Switching Waveforms Master Reset10 Switching WaveformsAddress CLKData OUT LatencyRead-to-Write-to-Read OE = Bank Select Read 17Address B1 Read No Operation WriteRead with Address Counter Advance23 Read-to-Write-to-Read OE Controlled19, 20, 21Cntld Cntinc DataoutAddress Internal Write with Address Counter Advance 24Write External Write with Counter HoldCounter Write Read Reset Address Counter Reset 21, 26Data Data OUT Address nLoad and Read Address Counter28 Cntrd InternalLoad Read Data with Counter External Address Internal Mkld Load and Read Mask RegisterMkrd Mask Internal Value Load Read Mask Register ValuePort 1 Write to Port 2 Read34, 35 Mailbox Interrupt Timing40, 41, 42, 43 Counter Interrupt 37, 38Operation Mode OperationInterrupts Master ResetInterrupt Operation Example Port FunctionAddress Counter Control Operations Cntrd MkrdCntinc = Cntld = Cntrst = CLK Counter-Mask Register Test Access Port TAP-Test Clock TCK Disabling the Jtag FeatureTest Mode Select Performing a TAP ResetNon-Debug Mode Go-NoGo Identification ID RegisterTAP Instruction Set Mbist Control States Debug ModeBoundary Scan Cells BSC P4IO17-9EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram FSM53MUX JTAG/BIST TAP Controller Block DiagramMbist Debug Register MDR 391 Bist TAP ControllerInstruction Identification Codes Description Scan Registers Sizes Register Name Bit SizePlaces the bypass register BYR between TDI and TDO Between TDI and TDOMbist Control Register MCR MCR10 Mode CE0 Boundary Scan Order Cell # Signal Name Bump Ball IDCLKP4 CLKP3CLKP2 Ordering Information Lead Pbga 27 x 27 x 2.33 mm BG272 Package DiagramDocument History Issue Orig. Description of Change DateSZV FSG