Cypress CY7C0430BV, CY7C0430CV manual CLKP2

Page 34

CY7C0430BV

CY7C0430CV

Table 9. Boundary Scan Order (continued)

Cell #

 

 

 

Signal Name

Bump (Ball) ID

 

 

 

 

166

 

IO2_P1

Y5

 

 

 

 

168

 

IO3_P1

W5

 

 

 

 

170

 

IO4_P1

Y4

 

 

 

 

172

 

IO5_P1

W4

 

 

 

 

174

 

IO6_P1

Y3

 

 

 

 

176

 

IO7_P1

W3

 

 

 

 

178

 

IO8_P1

Y2

 

 

 

 

180

 

IO0_P2

V9

 

 

 

 

182

 

IO1_P2

Y10

 

 

 

 

184

 

IO2_P2

W9

 

 

 

 

186

 

IO3_P2

Y9

 

 

 

 

188

 

IO4_P2

W8

 

 

 

 

190

 

IO5_P2

Y8

 

 

 

 

192

 

IO6_P2

V6

 

 

 

 

194

 

IO7_P2

Y7

 

 

 

 

196

 

IO8_P2

W7

 

 

 

 

198

 

A0_P2

L1

 

 

 

 

200

 

A1_P2

M2

 

 

 

 

202

 

A2_P2

M3

 

 

 

 

204

 

A3_P2

N1

 

 

 

 

206

 

A4_P2

N2

 

 

 

 

208

 

A5_P2

P2

 

 

 

 

210

 

A6_P2

P3

 

 

 

 

212

 

A7_P2

R1

 

 

 

 

214

 

A8_P2

R2

 

 

 

 

216

 

A9_P2

R3

 

 

 

 

218

 

A10_P2

T1

 

 

 

 

220

 

A11_P2

T2

 

 

 

 

222

 

A12_P2

U2

 

 

 

 

224

 

A13_P2

U3

 

 

 

 

226

 

A14_P2

V1

 

 

 

 

228

 

A15_P2

V2

 

 

 

 

 

 

 

 

 

 

 

230

 

 

 

 

 

 

 

 

_P2

R4

CNTINT

232

 

 

 

 

 

 

 

 

 

 

_P2

L3

CNTRST

234

 

 

 

 

_P2

N3

MKLD

236

 

 

 

 

 

 

_P2

N4

CNTLD

238

 

 

 

 

 

 

 

 

 

_P2

P4

CNTINC

240

 

 

 

 

 

 

 

_P2

T4

CNTRD

242

 

 

 

 

 

_P2

T3

MKRD

244

 

 

_P2

Y1

LB

246

 

 

 

_P2

W2

UB

Table 9. Boundary Scan Order (continued)

Cell #

 

 

 

 

 

Signal Name

Bump (Ball) ID

 

 

 

 

 

 

 

 

248

 

 

 

 

 

_P2

U4

OE

250

 

 

 

 

 

 

 

_P2

V5

R/W

252

 

CE1_P2

V3

 

 

 

 

 

 

 

 

254

 

 

 

 

 

 

 

 

_P2

V4

CE0

256

 

 

 

 

 

 

_P2

L2

INT

258

 

CLK_P2

M4

 

 

 

 

260

 

A0_P1

K1

 

 

 

 

262

 

A1_P1

J2

 

 

 

 

264

 

A2_P1

J3

 

 

 

 

266

 

A3_P1

H1

 

 

 

 

268

 

A4_P1

H2

 

 

 

 

270

 

A5_P1

G2

 

 

 

 

272

 

A6_P1

G3

 

 

 

 

274

 

A7_P1

F1

 

 

 

 

276

 

A8_P1

F2

 

 

 

 

278

 

A9_P1

F3

 

 

 

 

280

 

A10_P1

E1

 

 

 

 

282

 

A11_P1

E2

 

 

 

 

284

 

A12_P1

D2

 

 

 

 

286

 

A13_P1

D3

 

 

 

 

288

 

A14_P1

C1

 

 

 

 

290

 

A15_P1

C2

 

 

 

 

 

 

 

 

 

 

 

292

 

 

 

 

 

 

 

 

 

 

 

 

 

_P1

F4

CNTINT

294

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_P1

K3

CNTRST

296

 

 

 

 

 

 

 

 

 

_P1

H3

MKLD

298

 

 

 

 

 

 

 

 

 

 

 

_P1

H4

CNTLD

300

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_P1

G4

CNTINC

302

 

 

 

 

 

 

 

 

 

 

 

 

_P1

E4

CNTRD

304

 

 

 

 

 

 

 

 

 

 

_P1

E3

MKRD

306

 

 

 

_P1

A1

LB

308

 

 

 

 

_P1

B2

UB

310

 

 

 

 

 

_P1

D4

OE

312

 

 

 

 

 

 

 

_P1

C5

R/W

314

 

CE1_P1

C3

 

 

 

 

 

316

 

 

 

 

 

 

 

 

_P1

C4

CE0

318

 

 

 

 

 

 

_P1

K2

INT

320

 

CLK_P1

K4

 

 

 

 

322

 

IO9_P2

A6

 

 

 

 

324

 

IO10_P2

B6

 

 

 

 

326

 

IO11_P2

A5

 

 

 

 

328

 

IO12_P2

B5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-06027 Rev. *B

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Contents QuadPort DSE Family Applications FeaturesCypress Semiconductor Corporation Processor Processed Data Path Functional DescriptionProcessor Pre-processed Data Path Queue #1Top Level Logic Block Diagram Port 1 Operation-control Logic Blocks2Port 1 Operation-Control Logic Block Diagram Address Readback is independent of CEsPin Configuration Ball Grid Array BGA Top ViewCY7C0430CV Unit Selection GuidePin Definitions Port DescriptionMask Register Readback Input . When asserted LOW Counter Interrupt Flag Output . Flag is asserted LOWOperating Range Electrical Characteristics Over the Operating RangeMaximum Ratings CapacitanceNormal Load Three-State DelayAC Test Load TAP LoadOutput Enable to Data Valid Chip Enable Set-up TimeChip Enable Hold Time Maximum FrequencyJtag Timing and Switching Waveforms Switching Waveforms Master Reset10Data OUT CLKAddress LatencyAddress B1 Bank Select Read 17Read-to-Write-to-Read OE = Read No Operation WriteCntld Cntinc Read-to-Write-to-Read OE Controlled19, 20, 21Read with Address Counter Advance23 DataoutWrite External Write with Write with Address Counter Advance 24Address Internal Counter HoldData Data OUT Counter Reset 21, 26Counter Write Read Reset Address Address nCntrd Internal Load and Read Address Counter28Load Read Data with Counter External Address Internal Mkrd Mask Internal Value Load and Read Mask RegisterMkld Load Read Mask Register ValuePort 1 Write to Port 2 Read34, 35 Counter Interrupt 37, 38 Mailbox Interrupt Timing40, 41, 42, 43Mode Operation OperationInterrupt Operation Example Master ResetInterrupts Port FunctionCntrd Mkrd Address Counter Control OperationsCntinc = Cntld = Cntrst = CLK Counter-Mask Register Test Mode Select Disabling the Jtag FeatureTest Access Port TAP-Test Clock TCK Performing a TAP ResetIdentification ID Register Non-Debug Mode Go-NoGoTAP Instruction Set Boundary Scan Cells BSC Debug ModeMbist Control States P4IO17-9TAP Controller State Diagram FSM53 EXIT2-IR UPDATE-DR UPDATE-IRMbist Debug Register MDR 391 JTAG/BIST TAP Controller Block DiagramMUX Bist TAP ControllerPlaces the bypass register BYR between TDI and TDO Scan Registers Sizes Register Name Bit SizeInstruction Identification Codes Description Between TDI and TDOMbist Control Register MCR MCR10 Mode CLKP4 Boundary Scan Order Cell # Signal Name Bump Ball IDCE0 CLKP3CLKP2 Ordering Information Package Diagram Lead Pbga 27 x 27 x 2.33 mm BG272SZV Issue Orig. Description of Change DateDocument History FSG
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