Cypress CY7C0430BV manual Debug Mode, Mbist Control States, Boundary Scan Cells BSC, P4IO17-9

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CY7C0430BV

CY7C0430CV

number of TCK cycles depending on the TCK and CLKBIST frequency.

tCYC[CLKBIST] ⋅

tCYC = -------------------------------------------- m + SPC

tCYC[TCK]

tCYC is total number of TCK cycles required to run MBIST. SPC is the Synchronization Padding Cycles (4–6 cycles).

m is a constant represents the number of read and write opera- tions required to run MBIST algorithms (31195136).

Once the entire MBIST sequence is completed, supplying extra TCK or CLKBIST cycles will have no effect on the MBIST controller state or the pass-fail status.

Debug Mode

With the CYBIST instruction loaded and the MCR loaded with the value of “01,” and the FSM transitions to RUN_TEST/IDLE state, the MBIST goes into CYBIST-debug mode. The debug mode will be used to provide complete failure analysis infor- mation at the board level. It is recommended that the user runs the non-debug mode first and then the debug mode in order to save test time and to set an upper bound on the number of scan outs that will be needed. The failure data will be scanned out automatically once a failure occurs using the JTAG TAP interface. The failure data will be represented by a 100-bit packet given below. The 100-bit Memory Debug Register (MDR) will be connected between TDI and TDO, and will be shifted out on TDO, which is synchronized to TCK.

Figure 3 is a representation of the 100-bit MDR packet. The packet follows a two-bit header that has a logic “1” value, and represents two TCK cycles. MDR[97:26] represent the BIST comparator values of all four ports (each port has 18 data lines). A value of “1” indicates a bit failure. The scanned out

data is from LSB to MSB. MDR[25:10] represent the failing address (MSB to LSB). The state of the BIST controller is scanned out using MDR[9:4]. Bit 2 is the Test Done bit. A “0” in bit 2 means test not complete. The user has to monitor this bit at every packet to determine if more failure packets need to be scanned out at the end of the BIST operations. If the value is “0” then BIST must be repeated to capture the next failing packet. If it is “1,” it means that the last failing packets have been scanned out. A trailer similar to the header represents the end of a packet.

MCR_SCAN

This instruction will connect the Memory BIST Control Register (MCR) between TDI and TDO. The default value (upon master reset) is “00.” Shift_DR state will allow modifying the MCR to extend the MBIST functionality.

MBIST Control States

Thirty-five states are listed in Table 7. Four data algorithms are used in debug mode: moving inversion (MIA), march_2 (M2A), checkerboard (CBA), and unique address algorithm (UAA). Only Port 1 can write MIA, M2A, and CBA data to the memory. All four ports can read any algorithm data from the QuadPort DSE device memory. Ports 2, 3, and 4 will only write UAA data.

Boundary Scan Cells (BSC)

Table 9 lists all QuadPort DSE family I/Os with their associated BSC. Note that the cells have even numbers. Every I/O has two boundary scan cells. Bidirectional signals (address lines, datalines) require two cells so that one (the odd cell) is used to control a three-state buffer. Input only and output only signals have an extra dummy cell (odd cells) that are used to ease device layout.

99

98

 

 

 

 

1

1

 

 

 

 

 

 

 

 

 

 

62

97

 

 

 

 

 

P4_IO(17-9)

P3_IO(17-9)

P2_IO(17-9)

P1_IO(17-9)

 

 

 

 

 

 

 

61

 

 

 

 

26

 

P4_IO(8-0)

P3_IO(8-0)

P2_IO(8-0)

P1_IO(8-0)

 

 

 

 

 

 

 

2510

A(15-0)

94

MBIST_State

3

P/F

2

TD

10

1 1

Figure 3. MBIST Debug Register Packet

Document #: 38-06027 Rev. *B

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Contents QuadPort DSE Family Applications FeaturesCypress Semiconductor Corporation Functional Description Processor Pre-processed Data PathProcessor Processed Data Path Queue #1Top Level Logic Block Diagram Port 1 Operation-control Logic Blocks2Port 1 Operation-Control Logic Block Diagram Address Readback is independent of CEsPin Configuration Ball Grid Array BGA Top ViewSelection Guide Pin DefinitionsCY7C0430CV Unit Port DescriptionMask Register Readback Input . When asserted LOW Counter Interrupt Flag Output . Flag is asserted LOWElectrical Characteristics Over the Operating Range Maximum RatingsOperating Range CapacitanceThree-State Delay AC Test LoadNormal Load TAP LoadChip Enable Set-up Time Chip Enable Hold TimeOutput Enable to Data Valid Maximum FrequencyJtag Timing and Switching Waveforms Switching Waveforms Master Reset10CLK AddressData OUT LatencyBank Select Read 17 Read-to-Write-to-Read OE =Address B1 Read No Operation WriteRead-to-Write-to-Read OE Controlled19, 20, 21 Read with Address Counter Advance23Cntld Cntinc DataoutWrite with Address Counter Advance 24 Address InternalWrite External Write with Counter HoldCounter Reset 21, 26 Counter Write Read Reset AddressData Data OUT Address nCntrd Internal Load and Read Address Counter28Load Read Data with Counter External Address Internal Load and Read Mask Register MkldMkrd Mask Internal Value Load Read Mask Register ValuePort 1 Write to Port 2 Read34, 35 Counter Interrupt 37, 38 Mailbox Interrupt Timing40, 41, 42, 43Mode Operation OperationMaster Reset InterruptsInterrupt Operation Example Port FunctionCntrd Mkrd Address Counter Control OperationsCntinc = Cntld = Cntrst = CLK Counter-Mask Register Disabling the Jtag Feature Test Access Port TAP-Test Clock TCKTest Mode Select Performing a TAP ResetIdentification ID Register Non-Debug Mode Go-NoGoTAP Instruction Set Debug Mode Mbist Control StatesBoundary Scan Cells BSC P4IO17-9TAP Controller State Diagram FSM53 EXIT2-IR UPDATE-DR UPDATE-IRJTAG/BIST TAP Controller Block Diagram MUXMbist Debug Register MDR 391 Bist TAP ControllerScan Registers Sizes Register Name Bit Size Instruction Identification Codes DescriptionPlaces the bypass register BYR between TDI and TDO Between TDI and TDOMbist Control Register MCR MCR10 Mode Boundary Scan Order Cell # Signal Name Bump Ball ID CE0CLKP4 CLKP3CLKP2 Ordering Information Package Diagram Lead Pbga 27 x 27 x 2.33 mm BG272Issue Orig. Description of Change Date Document HistorySZV FSG
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