Cypress CY7C0430BV manual Selection Guide, Pin Definitions, CY7C0430CV Unit, Port Description

Page 6

CY7C0430BV

CY7C0430CV

Selection Guide

 

CY7C0430CV

CY7C0430CV

Unit

 

–133

–100

 

 

 

 

f

133[1]

100

MHz

MAX2

 

 

 

Max Access Time (Clock to Data)

4.2

5.0

ns

 

 

 

 

Max Operating Current ICC

750

600

mA

Max Standby Current for ISB1 (All ports TTL Level)

200

150

mA

Max Standby Current for ISB3 (All ports CMOS Level)

15

15

mA

Pin Definitions

 

 

 

 

 

Port 1

 

 

 

 

 

Port 2

 

 

 

 

 

Port 3

 

 

 

 

 

Port 4

Description

 

 

 

 

 

 

 

 

 

 

A0P1–A15P1

 

A0P2–A15P2

 

A0P3–A15P3

 

A0P4–A15P4

Address Input/Output.

 

I/O0P1–I/O17P1

I/O0P2–I/O17P2

I/O0P3–I/O17P3

I/O0P4–I/O17P4

Data Bus Input/Output.

 

CLKP1

 

CLKP2

 

CLKP3

 

CLKP4

Clock Input. This input can be free running or strobed.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Maximum clock input rate is fMAX.

 

 

 

P1

 

 

 

P2

 

 

 

P3

 

 

 

P4

Lower Byte Select Input. Asserting this signal LOW

 

LB

LB

LB

LB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

enables read and write operations to the lower byte. For

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

read operations both the LB and OE signals must be

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

asserted to drive output data on the lower byte of the data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pins.

 

 

 

 

P1

 

 

 

 

P2

 

 

 

 

P3

 

 

 

 

P4

Upper Byte Select Input. Same function as

 

 

but to the

 

UB

UB

UB

UB

LB,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

upper byte.

 

 

 

 

0P1,CE1P1

 

 

 

 

0P2,CE1P2

 

 

 

 

0P3,CE1P3

 

 

 

 

0P4,CE1P4

Chip Enable Input. To select any port, both

 

 

0 AND

 

CE

CE

CE

CE

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE1 must be asserted to their active states (CE0 ≤ VIL and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE1 ≥ VIH).

 

 

 

 

 

P1

 

 

 

 

 

P2

 

 

 

 

 

P3

 

 

 

 

 

P4

Output Enable Input. This signal must be asserted LOW

 

OE

OE

OE

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

to enable the I/O data lines during read operations. OE is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

asynchronous input.

 

 

 

 

 

 

P1

 

 

 

 

 

 

P2

 

 

 

 

 

 

P3

 

 

 

 

 

 

P4

Read/Write Enable Input. This signal is asserted LOW

 

R/W

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

to write to the dual port memory array. For read opera-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tions, assert this pin HIGH.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Master Reset Input. This is one signal for All Ports.

 

MRST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MRST is an asynchronous input. Asserting MRST LOW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

performs all of the reset functions as described in the text.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A MRST operation is required at power-up.

 

 

 

 

 

 

 

 

 

 

 

P1

 

 

 

 

 

 

 

 

 

 

P2

 

 

 

 

 

 

 

 

 

 

P3

 

 

 

 

 

 

 

 

 

 

P4

Counter Reset Input. Asserting this signal LOW resets

 

CNTRST

CNTRST

CNTRST

CNTRST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the burst address counter of its respective port to zero.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CNTRST is second to MRST in priority with respect to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

counter and mask register operations.

 

 

 

 

 

 

 

P1

 

 

 

 

 

 

 

P2

 

 

 

 

 

 

 

P3

 

 

 

 

 

 

 

P4

Mask Register Load Input. Asserting this signal LOW

 

MKLD

MKLD

MKLD

MKLD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

loads the mask register with the external address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

available on the address lines. MKLD operation has

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

higher priority over CNTLD operation.

 

 

 

 

 

 

 

 

 

P1

 

 

 

 

 

 

 

 

P2

 

 

 

 

 

 

 

 

P3

 

 

 

 

 

 

 

 

P4

Counter Load Input. Asserting this signal LOW loads the

 

CNTLD

CNTLD

CNTLD

CNTLD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

burst counter with the external address present on the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

address pins.

 

 

 

 

 

 

 

 

 

 

P1

 

 

 

 

 

 

 

 

 

P2

 

 

 

 

 

 

 

 

 

P3

 

 

 

 

 

 

 

 

 

P4

Counter Increment Input. Asserting this signal LOW

 

CNTINC

CNTINC

CNTINC

CNTINC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

increments the burst address counter of its respective port

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

on each rising edge of CLK.

Document #: 38-06027 Rev. *B

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Contents Features QuadPort DSE Family ApplicationsCypress Semiconductor Corporation Processor Processed Data Path Functional DescriptionProcessor Pre-processed Data Path Queue #1Top Level Logic Block Diagram Port 1 Operation-control Logic Blocks2Port 1 Operation-Control Logic Block Diagram Address Readback is independent of CEsPin Configuration Ball Grid Array BGA Top ViewCY7C0430CV Unit Selection GuidePin Definitions Port DescriptionMask Register Readback Input . When asserted LOW Counter Interrupt Flag Output . Flag is asserted LOWOperating Range Electrical Characteristics Over the Operating RangeMaximum Ratings CapacitanceNormal Load Three-State DelayAC Test Load TAP LoadOutput Enable to Data Valid Chip Enable Set-up TimeChip Enable Hold Time Maximum FrequencyJtag Timing and Switching Waveforms Switching Waveforms Master Reset10Data OUT CLKAddress LatencyAddress B1 Bank Select Read 17Read-to-Write-to-Read OE = Read No Operation WriteCntld Cntinc Read-to-Write-to-Read OE Controlled19, 20, 21Read with Address Counter Advance23 DataoutWrite External Write with Write with Address Counter Advance 24Address Internal Counter HoldData Data OUT Counter Reset 21, 26Counter Write Read Reset Address Address nLoad and Read Address Counter28 Cntrd InternalLoad Read Data with Counter External Address Internal Mkrd Mask Internal Value Load and Read Mask RegisterMkld Load Read Mask Register ValuePort 1 Write to Port 2 Read34, 35 Counter Interrupt 37, 38 Mailbox Interrupt Timing40, 41, 42, 43Mode Operation OperationInterrupt Operation Example Master ResetInterrupts Port FunctionAddress Counter Control Operations Cntrd MkrdCntinc = Cntld = Cntrst = CLK Counter-Mask Register Test Mode Select Disabling the Jtag FeatureTest Access Port TAP-Test Clock TCK Performing a TAP ResetNon-Debug Mode Go-NoGo Identification ID RegisterTAP Instruction Set Boundary Scan Cells BSC Debug ModeMbist Control States P4IO17-9TAP Controller State Diagram FSM53 EXIT2-IR UPDATE-DR UPDATE-IRMbist Debug Register MDR 391 JTAG/BIST TAP Controller Block DiagramMUX Bist TAP ControllerPlaces the bypass register BYR between TDI and TDO Scan Registers Sizes Register Name Bit SizeInstruction Identification Codes Description Between TDI and TDOMbist Control Register MCR MCR10 Mode CLKP4 Boundary Scan Order Cell # Signal Name Bump Ball IDCE0 CLKP3CLKP2 Ordering Information Package Diagram Lead Pbga 27 x 27 x 2.33 mm BG272SZV Issue Orig. Description of Change DateDocument History FSG
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