Cypress CY7C0430BV, CY7C0430CV manual Port 1 Write to Port 2 Read34, 35

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CY7C0430BV

CY7C0430CV

Switching Waveforms (continued)

Port 1 Write to Port 2 Read[34, 35, 36]

 

 

 

 

 

 

 

 

tCYC2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKP1

 

 

tCH2

 

 

 

 

 

 

 

tCL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PORT-1

 

 

 

 

 

 

 

 

 

 

 

 

tSA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

An

 

 

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/WP1

tSW

tHW

 

 

 

 

tCKHZ

tSD

tHD

tCKLZ

PORT-1

 

 

Dn

 

DATAIN

 

 

 

 

 

 

 

 

 

 

 

 

tCYC2

 

 

 

 

 

 

 

 

 

 

tCCS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKP2

 

 

 

 

 

 

 

 

 

 

 

tCL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCH2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PORT-2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA

 

 

 

 

 

 

 

 

 

 

 

 

 

tHA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

An

 

 

 

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/WP2

 

 

tCD2

PORT-2

Qn

DATAOUT

 

tDC

Notes:

34.CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = CNTINC =VIH.

35.This timing is valid when one port is writing, and one or more of the three other ports is reading the same location at the same time. If tCCS is violated, indeterminate data will be read out.

36.If tCCS< minimum specified value, then Port 2 will read the most recent data (written by Port 1) only (2*tCYC2 + tCD2) after the rising edge of Port 2’s clock. If tCCS > minimum specified value, then Port 2 will read the most recent data (written by Port 1) (tCYC2 + tCD2) after the rising edge of Port 2’s clock.

Document #: 38-06027 Rev. *B

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Contents Cypress Semiconductor Corporation FeaturesQuadPort DSE Family Applications Functional Description Processor Pre-processed Data PathProcessor Processed Data Path Queue #1Top Level Logic Block Diagram Port 1 Operation-control Logic Blocks2Port 1 Operation-Control Logic Block Diagram Address Readback is independent of CEsPin Configuration Ball Grid Array BGA Top ViewSelection Guide Pin DefinitionsCY7C0430CV Unit Port DescriptionMask Register Readback Input . When asserted LOW Counter Interrupt Flag Output . Flag is asserted LOWElectrical Characteristics Over the Operating Range Maximum RatingsOperating Range CapacitanceThree-State Delay AC Test LoadNormal Load TAP LoadChip Enable Set-up Time Chip Enable Hold TimeOutput Enable to Data Valid Maximum FrequencyJtag Timing and Switching Waveforms Switching Waveforms Master Reset10CLK AddressData OUT LatencyBank Select Read 17 Read-to-Write-to-Read OE =Address B1 Read No Operation WriteRead-to-Write-to-Read OE Controlled19, 20, 21 Read with Address Counter Advance23Cntld Cntinc DataoutWrite with Address Counter Advance 24 Address InternalWrite External Write with Counter HoldCounter Reset 21, 26 Counter Write Read Reset AddressData Data OUT Address nLoad Read Data with Counter External Address Internal Load and Read Address Counter28Cntrd Internal Load and Read Mask Register MkldMkrd Mask Internal Value Load Read Mask Register ValuePort 1 Write to Port 2 Read34, 35 Counter Interrupt 37, 38 Mailbox Interrupt Timing40, 41, 42, 43Mode Operation OperationMaster Reset InterruptsInterrupt Operation Example Port FunctionCntinc = Cntld = Cntrst = CLK Address Counter Control OperationsCntrd Mkrd Counter-Mask Register Disabling the Jtag Feature Test Access Port TAP-Test Clock TCKTest Mode Select Performing a TAP ResetTAP Instruction Set Non-Debug Mode Go-NoGoIdentification ID Register Debug Mode Mbist Control StatesBoundary Scan Cells BSC P4IO17-9TAP Controller State Diagram FSM53 EXIT2-IR UPDATE-DR UPDATE-IRJTAG/BIST TAP Controller Block Diagram MUXMbist Debug Register MDR 391 Bist TAP ControllerScan Registers Sizes Register Name Bit Size Instruction Identification Codes DescriptionPlaces the bypass register BYR between TDI and TDO Between TDI and TDOMbist Control Register MCR MCR10 Mode Boundary Scan Order Cell # Signal Name Bump Ball ID CE0CLKP4 CLKP3CLKP2 Ordering Information Package Diagram Lead Pbga 27 x 27 x 2.33 mm BG272Issue Orig. Description of Change Date Document HistorySZV FSG
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