Cypress CY7C0430BV, CY7C0430CV manual Port 1 Operation-Control Logic Block Diagram

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CY7C0430BV

CY7C0430CV

Port 1 Operation-Control Logic Block Diagram

(Address Readback is independent of CEs)

R/WP1

W

UBP1

CE0P1

CE1P1

LBP1

OEP1

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O9P1–I/O17P1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port-1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O0P1–I/O8P1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port 1

Readback

Register

MRST

A0P1–A15P1

16

Port 1

 

 

 

Mask Register

CNTRDP1

Priority

 

MKRDP1

 

Decision

 

MKLDP1

Port 1

CNTINCP1

Logic

Counter/

 

Address

 

 

Register

 

 

 

 

 

1

 

 

 

 

 

 

t

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

Port 1

P

 

64K × 18

 

 

Address

 

 

 

 

QuadPort

 

 

 

 

Decode

 

 

DSE Array

 

 

 

 

P ort 4

CNTLDP1

CNTRSTP1

CLKP1

MRST

CNTINTP1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LBP1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1

 

 

 

 

UB

Port 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/WP1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt

 

 

 

 

 

 

 

 

 

CE0P1

 

 

 

 

 

 

 

 

 

 

 

 

 

Logic

 

CE1P1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

P1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKP1

 

 

 

 

 

 

 

 

 

 

 

MRST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Po r t 2

INTP1

ort

3

 

P

 

Document #: 38-06027 Rev. *B

Page 4 of 37

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Contents QuadPort DSE Family Applications FeaturesCypress Semiconductor Corporation Functional Description Processor Pre-processed Data PathProcessor Processed Data Path Queue #1Top Level Logic Block Diagram Port 1 Operation-control Logic Blocks2Port 1 Operation-Control Logic Block Diagram Address Readback is independent of CEsPin Configuration Ball Grid Array BGA Top ViewSelection Guide Pin DefinitionsCY7C0430CV Unit Port DescriptionMask Register Readback Input . When asserted LOW Counter Interrupt Flag Output . Flag is asserted LOWElectrical Characteristics Over the Operating Range Maximum RatingsOperating Range CapacitanceThree-State Delay AC Test LoadNormal Load TAP LoadChip Enable Set-up Time Chip Enable Hold TimeOutput Enable to Data Valid Maximum FrequencyJtag Timing and Switching Waveforms Switching Waveforms Master Reset10CLK AddressData OUT LatencyBank Select Read 17 Read-to-Write-to-Read OE =Address B1 Read No Operation WriteRead-to-Write-to-Read OE Controlled19, 20, 21 Read with Address Counter Advance23Cntld Cntinc DataoutWrite with Address Counter Advance 24 Address InternalWrite External Write with Counter HoldCounter Reset 21, 26 Counter Write Read Reset AddressData Data OUT Address nCntrd Internal Load and Read Address Counter28Load Read Data with Counter External Address Internal Load and Read Mask Register MkldMkrd Mask Internal Value Load Read Mask Register ValuePort 1 Write to Port 2 Read34, 35 Counter Interrupt 37, 38 Mailbox Interrupt Timing40, 41, 42, 43Mode Operation OperationMaster Reset InterruptsInterrupt Operation Example Port FunctionCntrd Mkrd Address Counter Control OperationsCntinc = Cntld = Cntrst = CLK Counter-Mask Register Disabling the Jtag Feature Test Access Port TAP-Test Clock TCKTest Mode Select Performing a TAP ResetIdentification ID Register Non-Debug Mode Go-NoGoTAP Instruction Set Debug Mode Mbist Control StatesBoundary Scan Cells BSC P4IO17-9TAP Controller State Diagram FSM53 EXIT2-IR UPDATE-DR UPDATE-IRJTAG/BIST TAP Controller Block Diagram MUXMbist Debug Register MDR 391 Bist TAP ControllerScan Registers Sizes Register Name Bit Size Instruction Identification Codes DescriptionPlaces the bypass register BYR between TDI and TDO Between TDI and TDOMbist Control Register MCR MCR10 Mode Boundary Scan Order Cell # Signal Name Bump Ball ID CE0CLKP4 CLKP3CLKP2 Ordering Information Package Diagram Lead Pbga 27 x 27 x 2.33 mm BG272Issue Orig. Description of Change Date Document HistorySZV FSG