Cypress CY7C0430CV, CY7C0430BV Counter Interrupt 37, 38, Mailbox Interrupt Timing40, 41, 42, 43

Page 21

 

 

 

 

 

 

CY7C0430BV

 

 

 

 

 

 

CY7C0430CV

Switching Waveforms (continued)

 

 

 

 

 

Counter Interrupt [37, 38, 39]

 

 

 

 

 

 

 

tCYC2

 

 

 

 

 

 

tCH2

tCL2

 

 

 

 

 

CLK

 

 

 

 

 

 

 

EXTERNAL

007Fh

xx7Dh

 

 

 

 

 

ADDRESS

 

 

 

 

 

 

 

tSMLD

 

tHMLD

 

 

 

 

 

MKLD

 

 

 

 

 

 

 

CNTLD

 

tSCLD

tHCLD

 

 

 

 

 

 

 

 

 

 

 

CNTINC

 

 

tSCINC

tHCINC

 

 

 

 

 

 

 

 

 

 

COUNTER

 

 

 

 

 

 

 

INTERNAL

 

An

xx7Dh

xx7Eh

xx7Fh

xx00h

xx00h

ADDRESS

 

 

 

 

 

 

 

 

CNTINT

 

 

 

 

tSCINT

 

tRCINT

 

 

 

 

 

 

 

Mailbox Interrupt Timing[40, 41, 42, 43, 44]

 

 

 

 

 

 

tCYC2

 

 

 

 

 

 

tCH2

tCL2

 

 

 

 

 

CLKP1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA tHA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PORT-1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FFFE

 

 

 

 

 

 

 

 

 

An

 

 

 

 

 

 

An+1

 

 

 

 

 

 

 

 

 

 

An+2

 

 

 

 

 

 

An+3

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSINT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRINT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT

P2

tCYC2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKP2

 

 

tCH2

 

 

 

 

 

 

 

tCL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA

tHA

PORT-2

Am

ADDRESS

Am+1

FFFE

Am+3

Am+4

Notes:

37.CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTRD = MKRD = VIH.

38.CNTINT is always driven.

39.CNTINC goes LOW as the counter address masked portion is incremented from xx7Fh to xx00h. The “x” is “Don’t Care.”

40.CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = CNTRD = CNTINC = MKRD = MKLD =VIH.

41.Address “FFFE” is the mailbox location for Port 2.

42.Port 1 is configured for Write operation, and Port 2 is configured for Read operation.

43.Port 1 and Port 2 are used for simplicity. All four ports can write to or read from any mailbox.

44.Interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of the read clock.

Document #: 38-06027 Rev. *B

Page 21 of 37

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Contents Features QuadPort DSE Family ApplicationsCypress Semiconductor Corporation Processor Pre-processed Data Path Functional DescriptionProcessor Processed Data Path Queue #1Port 1 Operation-control Logic Blocks2 Top Level Logic Block DiagramAddress Readback is independent of CEs Port 1 Operation-Control Logic Block DiagramBall Grid Array BGA Top View Pin ConfigurationPin Definitions Selection GuideCY7C0430CV Unit Port DescriptionCounter Interrupt Flag Output . Flag is asserted LOW Mask Register Readback Input . When asserted LOWMaximum Ratings Electrical Characteristics Over the Operating RangeOperating Range CapacitanceAC Test Load Three-State DelayNormal Load TAP LoadChip Enable Hold Time Chip Enable Set-up TimeOutput Enable to Data Valid Maximum FrequencyJtag Timing and Switching Waveforms Master Reset10 Switching WaveformsAddress CLKData OUT LatencyRead-to-Write-to-Read OE = Bank Select Read 17Address B1 Read No Operation WriteRead with Address Counter Advance23 Read-to-Write-to-Read OE Controlled19, 20, 21Cntld Cntinc DataoutAddress Internal Write with Address Counter Advance 24Write External Write with Counter HoldCounter Write Read Reset Address Counter Reset 21, 26Data Data OUT Address nLoad and Read Address Counter28 Cntrd InternalLoad Read Data with Counter External Address Internal Mkld Load and Read Mask RegisterMkrd Mask Internal Value Load Read Mask Register ValuePort 1 Write to Port 2 Read34, 35 Mailbox Interrupt Timing40, 41, 42, 43 Counter Interrupt 37, 38Operation Mode OperationInterrupts Master ResetInterrupt Operation Example Port FunctionAddress Counter Control Operations Cntrd MkrdCntinc = Cntld = Cntrst = CLK Counter-Mask Register Test Access Port TAP-Test Clock TCK Disabling the Jtag FeatureTest Mode Select Performing a TAP ResetNon-Debug Mode Go-NoGo Identification ID RegisterTAP Instruction Set Mbist Control States Debug ModeBoundary Scan Cells BSC P4IO17-9EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram FSM53MUX JTAG/BIST TAP Controller Block DiagramMbist Debug Register MDR 391 Bist TAP ControllerInstruction Identification Codes Description Scan Registers Sizes Register Name Bit SizePlaces the bypass register BYR between TDI and TDO Between TDI and TDOMbist Control Register MCR MCR10 Mode CE0 Boundary Scan Order Cell # Signal Name Bump Ball IDCLKP4 CLKP3CLKP2 Ordering Information Lead Pbga 27 x 27 x 2.33 mm BG272 Package DiagramDocument History Issue Orig. Description of Change DateSZV FSG