Cypress CY7C0430BV, CY7C0430CV manual Mbist Control Register MCR MCR10 Mode

CY7C0430BV

CY7C0430CV

Table 7. MBIST Control States (continued)

States Code		State Name		Description
001001	chkr_r		All ports read topological checkerboard data.
001000	n_chkr_w		Port 1 write inverse topological checkerboard data.
011000	n_chkr_r		All ports read inverse topological checkerboard data.
011001	uaddr_zeros2		Port 2 write all zeros to memory using Unique Address Algorithm (UAA).
011011	uaddr_write2		Port 2 writes every address value into its memory location (UAA).
011010	uaddr_read2		All ports read UAA data.
011110	uaddr_ones2		Port 2 writes all ones to memory.
011111	n_uaddr_write2		Port 2 writes inverse address value into memory.
011101	n_uaddr_read2		All ports read inverse UAA data.
011001	uaddr_zeros3		Port 3 write all zeros to memory using Unique Address Algorithm (UAA).
011011	uaddr_write3		Port 3 writes every address value into its memory location (UAA).
011010	uaddr_read3		All ports read UAA data.
011110	uaddr_ones3		Port 3 writes all ones to memory.
011111	n_uaddr_write3		Port 3 writes inverse address value into memory.
011101	n_uaddr_read3		All ports read inverse UAA data.
011001	uaddr_zeros4		Port 4 write all zeros to memory using Unique Address Algorithm (UAA).
011011	uaddr_write4		Port 4 writes every address value into its memory location (UAA).
011010	uaddr_read4		All ports read UAA data.
011110	uaddr_ones4		Port 4 writes all ones to memory.
011111	n_uaddr_write4		Port 4 writes inverse address value into memory.
011101	n_uaddr_read4		All ports read inverse UAA data.
110010	complete		Test complete.
Table 8. MBIST Control Register (MCR)
MCR[1:0]		Mode
00		Non-Debug
01		Debug
10		Reserved
11		Reserved

Document #: 38-06027 Rev. *B Page 32 of 37

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