Cypress CY7C0430BV manual Maximum Ratings, Electrical Characteristics Over the Operating Range

Page 8

CY7C0430BV

CY7C0430CV

Maximum Ratings

(Above which the useful life may be impaired. For user guide- lines, not tested.)

Storage Temperature

–65°C to + 150°C

Ambient Temperature............................................with

–55°C to + 125°C

Power Applied

Supply Voltage to Ground Potential

–0.5V to + 4.6V

DC Voltage Applied to

 

Outputs in High-Z State

–0.5V to VCC + 0.5V

DC Input Voltage

–0.5V to VCC + 0.5V

Electrical Characteristics Over the Operating Range

Output Current into Outputs (LOW)

............................. 20 mA

Static Discharge Voltage

> 2200V

Latch-up Current

> 200 mA

Operating Range

Range

Ambient Temperature

VDD

Commercial

0°C to +70°C

3.3V ± 150 mV

 

 

 

Industrial

–40°C to +85°C

3.3V ± 150 mV

 

 

 

 

 

 

 

 

 

Quadport DSE Family

 

 

 

 

 

 

 

 

–133

 

 

 

 

–100

 

 

Parameter

 

 

Description

 

 

 

 

 

 

 

 

Unit

 

 

Min.

Typ.

 

Max.

Min.

 

Typ.

Max.

VOH

Output HIGH Voltage

2.4

 

 

 

2.4

 

 

 

V

 

(VCC = Min., IOH = –4.0 mA)

 

 

 

 

 

 

 

 

 

VOL

Output LOW Voltage

 

 

 

0.4

 

 

 

0.4

V

 

(VCC = Min., IOH = +4.0 mA)

 

 

 

 

 

 

 

 

 

VIH

Input HIGH Voltage

2.0

 

 

 

2.0

 

 

 

V

VIL

Input LOW Voltage

 

 

 

0.8

 

 

 

0.8

V

IOZ

Output Leakage Current

–10

 

 

10

–10

 

 

10

A

ICC

Operating Current (VCC = Max., IOUT = 0 mA)

 

350

 

700

 

 

300

550

mA

 

Outputs Disabled, CE = VIL, f = fmax

 

 

 

 

 

 

 

 

 

ISB1

Standby Current (four ports toggling at TTL

 

80

 

200

 

 

60

150

mA

 

Levels,0 active)

 

 

 

 

 

 

 

 

 

 

CE1-4VIH, f = fMAX

 

 

 

 

 

 

 

 

 

ISB2

Standby Current (four ports toggling at TTL

 

150

 

300

 

 

125

250

mA

 

Levels, 1 active) CE1 CE2 CE3 CE4 < VIL,

 

 

 

 

 

 

 

 

 

 

f = fMAX

 

 

 

 

 

 

 

 

 

ISB3

Standby Current (four ports CMOS Level, 0

 

1.5

 

15

 

 

1.5

15

mA

 

active)

CE

1–4VIH, f = 0

 

 

 

 

 

 

 

 

 

ISB4

Standby Current (four ports CMOS Level, 1

 

110

 

290

 

 

85

240

mA

 

active and toggling) CE1 CE2 CE3 CE4 <

 

 

 

 

 

 

 

 

 

 

VIL, f = fMAX

 

 

 

 

 

 

 

 

 

JTAG TAP Electrical Characteristics Over the Operating Range

 

 

 

 

 

 

 

Parameter

Description

Test Conditions

Min.

Max.

Unit

VOH1

Output HIGH Voltage

IOH = 4.0 mA

2.4

 

V

VOL1

Output LOW Voltage

IOL = 4.0 mA

 

0.4

V

VIH

Input HIGH Voltage

 

2.0

 

V

VIL

Input LOW Voltage

 

 

0.8

V

IX

Input Leakage Current

GND VI VDD

–100

100

A

Capacitance

 

Parameter

Description

Test Conditions

Max.

Unit

 

CIN (All Pins)

Input Capacitance

TA = 25°C, f = 1 MHz,

10

pF

 

 

 

VCC = 3.3V

 

 

 

COUT (All Pins)

Output Capacitance

10

pF

 

CIN (CLK Pins)

Input Capacitance

 

15

pF

 

COUT (CLK Pins)

Output Capacitance

 

15

pF

Document #: 38-06027 Rev. *B

 

 

Page 8 of 37

[+] Feedback

Image 8
Contents Cypress Semiconductor Corporation FeaturesQuadPort DSE Family Applications Functional Description Processor Pre-processed Data PathProcessor Processed Data Path Queue #1Top Level Logic Block Diagram Port 1 Operation-control Logic Blocks2Port 1 Operation-Control Logic Block Diagram Address Readback is independent of CEsPin Configuration Ball Grid Array BGA Top ViewSelection Guide Pin DefinitionsCY7C0430CV Unit Port DescriptionMask Register Readback Input . When asserted LOW Counter Interrupt Flag Output . Flag is asserted LOWElectrical Characteristics Over the Operating Range Maximum RatingsOperating Range CapacitanceThree-State Delay AC Test LoadNormal Load TAP LoadChip Enable Set-up Time Chip Enable Hold TimeOutput Enable to Data Valid Maximum FrequencyJtag Timing and Switching Waveforms Switching Waveforms Master Reset10CLK AddressData OUT LatencyBank Select Read 17 Read-to-Write-to-Read OE =Address B1 Read No Operation WriteRead-to-Write-to-Read OE Controlled19, 20, 21 Read with Address Counter Advance23Cntld Cntinc DataoutWrite with Address Counter Advance 24 Address InternalWrite External Write with Counter HoldCounter Reset 21, 26 Counter Write Read Reset AddressData Data OUT Address nLoad Read Data with Counter External Address Internal Load and Read Address Counter28Cntrd Internal Load and Read Mask Register MkldMkrd Mask Internal Value Load Read Mask Register ValuePort 1 Write to Port 2 Read34, 35 Counter Interrupt 37, 38 Mailbox Interrupt Timing40, 41, 42, 43Mode Operation OperationMaster Reset InterruptsInterrupt Operation Example Port FunctionCntinc = Cntld = Cntrst = CLK Address Counter Control OperationsCntrd Mkrd Counter-Mask Register Disabling the Jtag Feature Test Access Port TAP-Test Clock TCKTest Mode Select Performing a TAP ResetTAP Instruction Set Non-Debug Mode Go-NoGoIdentification ID Register Debug Mode Mbist Control StatesBoundary Scan Cells BSC P4IO17-9TAP Controller State Diagram FSM53 EXIT2-IR UPDATE-DR UPDATE-IRJTAG/BIST TAP Controller Block Diagram MUXMbist Debug Register MDR 391 Bist TAP ControllerScan Registers Sizes Register Name Bit Size Instruction Identification Codes DescriptionPlaces the bypass register BYR between TDI and TDO Between TDI and TDOMbist Control Register MCR MCR10 Mode Boundary Scan Order Cell # Signal Name Bump Ball ID CE0CLKP4 CLKP3CLKP2 Ordering Information Package Diagram Lead Pbga 27 x 27 x 2.33 mm BG272Issue Orig. Description of Change Date Document HistorySZV FSG