Connect Tech PCI-104 user manual RS-485 Port 2 Pinout P6 Signal Direction

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Connect Tech FreeForm/PCI-104 User Manual

								Top View
		2			4				26 28
	High Speed	Serial
	P4

		1			3				25 27
RS-485 Headers (P5, P6)
				Table 7: RS-485 Port 1 Pinout (P5)
	Pin			Signal				Direction
	1			RXD+1			Input
	2								1
	2								1
	3			RXD-1			Input
	4															10
	5			TXD+1			Output									10
	5			TXD+1			Output
													P5
	6												P5
	7			TXD-1			Output						485 Port 0
	7			TXD-1			Output
	8											Top View
	9			GND			Power
	10
				Table 8: RS-485 Port 2 Pinout (P6)
	Pin			Signal				Direction
	1			RXD+2				Input
	2								10					P6
	2
	3			RXD-2				Input
	3			RXD-2				Input						485 Port 1
	4													485 Port 1
	4
	5			TXD+2				Output									1
	5			TXD+2				Output									1
	6
	7			TXD-2				Output				Top View
	8											Top View
	8
	9			GND				Power
	10

Revision 0.02

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Contents FreeForm/PCI-104 Copyright Notice Limited Lifetime WarrantyTrademark Acknowledgment Contact Information Customer Support OverviewTelephone/Facsimile Email/InternetTable of Contents List of Figures List of TablesIntroduction Product FeaturesAbout this manual System Overview FreeForm/PCI-104 Block DiagramComponents Jumpers /Switches DescriptionReference Design Slot Selection RSW1 Position Fpga Configuration Settings J1 Jumpers and SwitchesFpga Configuration Settings J1 Location Function Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header P7 Gpio Header Pinout Signal DirectionExternal Power Connector Pinout P8 Signal Direction Side View External Power Connector P8Connector’s Mating Components and Cables Heat Sink Installation Hardware InstallationStand-alone Operation Fpga Development Environment Software InstallationPLX Software Development Kit SDK Reference Design & Application ExamplesFpga Configuration Reference Design Fpga power analysis Power and Thermal ConsiderationsSpecifications Launch Impact Appendix a iMPACT Instructions for Fpga ConfigurationPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga / SPI flash Association Configuring the Fpga with the SPI FlashPage Programming the Flash Elapsed time = Scenario 1 Heatsink attached, 250 LFM Appendix B Power calculationsScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Revision B Local Clock Generation Reference DesignDDR2 Pinout Revision CHardware Description Connector PinoutsRevision B Revision C Revision B Revision C Power Requirements SpecificationsRevision B