Connect Tech PCI-104 user manual Revision

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Connect Tech FreeForm/PCI-104 User Manual

6)

Click “No” when asked if another device is to be ad ded.

Click “OK” to accept the setup.

7)

Double Click “Generate File” from the “iMPACT” proc

esses menu. The status will be reported in

 

the console.

 

//*** BATCH CMD : setMode -pff

//*** BATCH CMD : setSubmode -pffparallel

//*** BATCH CMD : setAttribute -configdevice -attr fillValue -value "FF"

//*** BATCH CMD : setAttribute -configdevice -attr swapBit -value "true"

//*** BATCH CMD : setAttribute -configdevice -attr fileFormat -value "mcs"

//*** BATCH CMD : setAttribute -configdevice -attr dir -value "UP"

//*** BATCH CMD : setAttribute -configdevice -attr path -value

"C:\Data\Projects\FreeFormPCI104\hardware\logic\init_plx_GPIO25\/"

//*** BATCH CMD : setAttribute -configdevice -attr name -value "init_plx_GPIO25.cs" Total configuration bit size = 9371136 bits.

Total configuration byte size = 1171392 bytes.

//*** BATCH CMD : setCurrentDesign -version 0

//*** BATCH CMD : generate -spi

Swap bit can only be disabled in Hex file format only. 0x11dfc0 (1171392) bytes loaded up from 0x0

Using user-specified prom size of 2048K Writing file "C:\Data\Projects\FreeFormPCI104\hardware\logic\init_plx_GPIO25\//init_plx_GPIO25.mcs"

.

Writing file

"C:\Data\Projects\FreeFormPCI104\hardware\logic\init_plx_GPIO25\//init_plx_GPIO25.prm"

.

Revision 0.02

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Contents FreeForm/PCI-104 Copyright Notice Limited Lifetime WarrantyTrademark Acknowledgment Customer Support Overview Contact InformationTelephone/Facsimile Email/InternetTable of Contents List of Tables List of FiguresIntroduction Product FeaturesAbout this manual FreeForm/PCI-104 Block Diagram System OverviewJumpers /Switches Description ComponentsReference Design Jumpers and Switches Slot Selection RSW1 Position Fpga Configuration Settings J1Fpga Configuration Settings J1 Location Function Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header Pinout Signal Direction Gpio Header P7Side View External Power Connector P8 External Power Connector Pinout P8 Signal DirectionConnector’s Mating Components and Cables Heat Sink Installation Hardware InstallationStand-alone Operation Software Installation Fpga Development EnvironmentPLX Software Development Kit SDK Reference Design & Application ExamplesFpga Configuration Power and Thermal Considerations Reference Design Fpga power analysisSpecifications Appendix a iMPACT Instructions for Fpga Configuration Launch ImpactPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga with the SPI Flash Configuring the Fpga / SPI flash AssociationPage Programming the Flash Elapsed time = Appendix B Power calculations Scenario 1 Heatsink attached, 250 LFMScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Reference Design Revision B Local Clock GenerationDDR2 Pinout Revision CHardware Description Connector PinoutsRevision B Revision C Revision B Revision C Power Requirements SpecificationsRevision B