Connect Tech PCI-104 user manual Configuring the Fpga with the SPI Flash

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Connect Tech FreeForm/PCI-104 User Manual

Configuring the FPGA with the SPI Flash

In previous Xilinx FPGA configurations, the SPI flash required programming via 3rd party JTAG test software or through in-system methods. The following features are new to ISE 9.1/9.2, and are only available on select FPGAs, including the Virtex-5. Your FreeForm/PCI-104 card featuring the Xilinx Virtex-5 FPGA includes a standard core to enable programming of BPI and SPI flashes over JTAG.

Configuring the FPGA / SPI flash Association

1) Select “Boundary Scan” from the “Flows” tab.

2) Right click on the FPGA and select “Add SPI Flash…”

Revision 0.02

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Contents FreeForm/PCI-104 Trademark Acknowledgment Limited Lifetime WarrantyCopyright Notice Contact Information Customer Support OverviewTelephone/Facsimile Email/InternetTable of Contents List of Figures List of TablesAbout this manual Product FeaturesIntroduction System Overview FreeForm/PCI-104 Block DiagramComponents Jumpers /Switches DescriptionReference Design Slot Selection RSW1 Position Fpga Configuration Settings J1 Jumpers and SwitchesFpga Configuration Settings J1 Location Function Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header P7 Gpio Header Pinout Signal DirectionExternal Power Connector Pinout P8 Signal Direction Side View External Power Connector P8Connector’s Mating Components and Cables Stand-alone Operation Hardware InstallationHeat Sink Installation Fpga Development Environment Software InstallationPLX Software Development Kit SDK Reference Design & Application ExamplesFpga Configuration Reference Design Fpga power analysis Power and Thermal ConsiderationsSpecifications Launch Impact Appendix a iMPACT Instructions for Fpga ConfigurationPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga / SPI flash Association Configuring the Fpga with the SPI FlashPage Programming the Flash Elapsed time = Scenario 1 Heatsink attached, 250 LFM Appendix B Power calculationsScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Revision B Local Clock Generation Reference DesignDDR2 Pinout Revision CRevision B Revision C Connector PinoutsHardware Description Revision B SpecificationsRevision B Revision C Power Requirements