Connect Tech PCI-104 user manual Jumpers /Switches Description, Components

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Connect Tech FreeForm/PCI-104 User Manual

Figure 2: FreeForm/PCI-104 Layout

Table 1: FreeForm/PCI-104 Components

	Connectors	Description
	P1	PCI-104 connector
	P2	JTAG programming header
	P3	SPI flash programming header
	P4	High-speed serial connector
	P5, P6	RS-485 header
	P7	GPIO header
	P8	External power header
	P9	RJ-45 A
	P10	RJ-45 B

	Jumpers /Switches	Description
	RSW1	Slot selection
	J1	FPGA configuration settings
	Components	Description (not all on top side)
	D1-D4	User LEDs
	D5	FPGA load complete LED
	U4	PLX PCI-local bus bridge
	U5	Virtex-5 FPGA
	U10	FPGA configuration flash
	U11	Embedded code flash
	U12, U13	DDR2 memory
	U14	Parameter EEPROM
	U15, U16	RS-485 transceiver
	U17	Dual 10/100 PHY
	O1,O2, O3	Oscillators

Revision 0.02

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Contents FreeForm/PCI-104 Trademark Acknowledgment Limited Lifetime WarrantyCopyright Notice Customer Support Overview Contact InformationTelephone/Facsimile Email/InternetTable of Contents List of Tables List of FiguresAbout this manual Product FeaturesIntroduction FreeForm/PCI-104 Block Diagram System OverviewJumpers /Switches Description ComponentsReference Design Jumpers and Switches Slot Selection RSW1 Position Fpga Configuration Settings J1Fpga Configuration Settings J1 Location Function Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header Pinout Signal Direction Gpio Header P7Side View External Power Connector P8 External Power Connector Pinout P8 Signal DirectionConnector’s Mating Components and Cables Stand-alone Operation Hardware InstallationHeat Sink Installation Software Installation Fpga Development EnvironmentPLX Software Development Kit SDK Reference Design & Application ExamplesFpga Configuration Power and Thermal Considerations Reference Design Fpga power analysisSpecifications Appendix a iMPACT Instructions for Fpga Configuration Launch ImpactPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga with the SPI Flash Configuring the Fpga / SPI flash AssociationPage Programming the Flash Elapsed time = Appendix B Power calculations Scenario 1 Heatsink attached, 250 LFMScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Reference Design Revision B Local Clock GenerationDDR2 Pinout Revision CRevision B Revision C Connector PinoutsHardware Description Revision B SpecificationsRevision B Revision C Power Requirements