Connect Tech PCI-104 Hardware Installation, Heat Sink Installation, Stand-alone Operation

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Connect Tech FreeForm/PCI-104 User Manual

Hardware Installation

Before installing the FreeForm/PCI-104 into a PCI-104 stack, ensure the following:

oSlot selection is properly set using the rotary switch RSW1. o FPGA configuration jumper J1 is set to read from flash.

Once installed in the system and power is applied, the LED D1 will illuminate to indicate that FreeForm/PCI-104 is functioning.

Heat Sink Installation

Each FreeForm/PCI-104 ships with a FPGA heat sink (27 mm x 27 mm); to be installed by the user. Simply peel of the sticker backing and press firmly onto the FPGA, using proper ESD precautions.

If the heat sink size is not suitable for your application, please contact Connect Tech Inc.

WARNING In many applications, including high speed memory operations, the FPGA dissipates a significant amount of power. Failure to use any heat sinking will result in the product warranty being voided.

Stand-alone Operation

Operating the FreeForm/PCI-104 outside of a PCI-104 stack or a PCI system for extended periods of time is not recommended. The PCI to local bus bridge (PCI PLX 9056) requires the pull-up/pull-down resistors provided on a system’s main board.

Configuring or programming the FreeForm/PCI-104 in stand-alone mode is acceptable, providing that it is not left powered on in stand-alone state for an extended period of time.

WARNING The power supply MSG037 included with the development kit DEV002 is intended for desktop programming only. It is not intended or warranted to be used in any other situation.

Revision 0.02

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Contents FreeForm/PCI-104 Trademark Acknowledgment Limited Lifetime WarrantyCopyright Notice Contact Information Customer Support OverviewTelephone/Facsimile Email/InternetTable of Contents List of Figures List of TablesAbout this manual Product FeaturesIntroduction System Overview FreeForm/PCI-104 Block DiagramComponents Jumpers /Switches DescriptionReference Design Slot Selection RSW1 Position Fpga Configuration Settings J1 Jumpers and SwitchesFpga Configuration Settings J1 Location Function Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header P7 Gpio Header Pinout Signal DirectionExternal Power Connector Pinout P8 Signal Direction Side View External Power Connector P8Connector’s Mating Components and Cables Stand-alone Operation Hardware InstallationHeat Sink Installation Fpga Development Environment Software InstallationPLX Software Development Kit SDK Reference Design & Application ExamplesFpga Configuration Reference Design Fpga power analysis Power and Thermal ConsiderationsSpecifications Launch Impact Appendix a iMPACT Instructions for Fpga ConfigurationPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga / SPI flash Association Configuring the Fpga with the SPI FlashPage Programming the Flash Elapsed time = Scenario 1 Heatsink attached, 250 LFM Appendix B Power calculationsScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Revision B Local Clock Generation Reference DesignDDR2 Pinout Revision CRevision B Revision C Connector PinoutsHardware Description Revision B SpecificationsRevision B Revision C Power Requirements
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