Connect Tech PCI-104 user manual Specifications

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Connect Tech FreeForm/PCI-104 User Manual

Specifications

Programmable FPGA	Virtex-5 FPGA LX30T

Input Clock	100MHz

Memory / Flash	128MB DDR2-400
	2MB Flash – FPGA configuration
	8MB Flash – Embedded code
	4K serial EEPROM – parameter storage

General Purpose User I/O	64 single ended I/O
	32 LVDS I/O

Serial	2 x RS-485

Ethernet	2 x 10Base-T, 100Base-TX

High-speed serial	4 x Rocket I/O transceivers (GTP)

Operating Environment	Storage Temperature:
	-65°C to 150°C
	Operating Temperature:
	0°C to 70°C	(commercial)
	-40°C to 85°C	(industrial)

Power Requirements	+5V DC, in PCI-104 stack
	+5V DC standalone
	Current requirements are configuration dependant

Dimensions	PC/104-Plus2.2 compliant
	PCI-104 1.0 compliant

Connectors	Two RJ-45 modular jacks (Ethernet)
	Two 2x5 0.100” headers (serial)
	One 2x40 0.050 x 0.100” header (general I/O)
	One 1x6 0.100” header (flash programming)
	One 2x14 0.8 mm differential pair terminal (high speed serial)

Revision 0.02

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Contents FreeForm/PCI-104 Limited Lifetime Warranty Copyright NoticeTrademark Acknowledgment Contact Information Customer Support OverviewTelephone/Facsimile Email/InternetTable of Contents List of Figures List of TablesProduct Features IntroductionAbout this manual System Overview FreeForm/PCI-104 Block DiagramComponents Jumpers /Switches DescriptionReference Design Slot Selection RSW1 Position Fpga Configuration Settings J1 Jumpers and SwitchesFpga Configuration Settings J1 Location Function Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header P7 Gpio Header Pinout Signal DirectionExternal Power Connector Pinout P8 Signal Direction Side View External Power Connector P8Connector’s Mating Components and Cables Hardware Installation Heat Sink InstallationStand-alone Operation Fpga Development Environment Software InstallationPLX Software Development Kit SDK Reference Design & Application ExamplesFpga Configuration Reference Design Fpga power analysis Power and Thermal ConsiderationsSpecifications Launch Impact Appendix a iMPACT Instructions for Fpga ConfigurationPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga / SPI flash Association Configuring the Fpga with the SPI FlashPage Programming the Flash Elapsed time = Scenario 1 Heatsink attached, 250 LFM Appendix B Power calculationsScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Revision B Local Clock Generation Reference DesignDDR2 Pinout Revision CConnector Pinouts Hardware DescriptionRevision B Revision C Specifications Revision B Revision C Power RequirementsRevision B