Connect Tech PCI-104 user manual Appendix C Hardware Changes from Revision B

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Connect Tech FreeForm/PCI-104 User Manual

Appendix C: Hardware Changes from Revision B

This appendix lists the changes between hardware revision B and hardware revision C. The following is a summary of changes:

￿PCB requires only 5V over PCI-104; it previously required 3.3V and 5V

￿A dedicated local bus oscillator was added to generate 50Mhz. A clock is no longer forwarded from FPGA to the PLX PCI 9056.

￿The DDR2 FPGA pinout has been changed to increase timing margins

￿The pinout of connector P4 (high-speed serial) has changed. The sideband signals have been relocated and 3.3V has been added.

￿The orientation of connector P5 (RS-485 port 0) has rotated 180 degrees

￿The Location of P8 (external power connector) has changed. The 3.3V enable signal has also been removed

Revision 0.02

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Contents FreeForm/PCI-104 Limited Lifetime Warranty Copyright NoticeTrademark Acknowledgment Customer Support Overview Contact InformationTelephone/Facsimile Email/InternetTable of Contents List of Tables List of FiguresProduct Features IntroductionAbout this manual FreeForm/PCI-104 Block Diagram System OverviewJumpers /Switches Description ComponentsReference Design Jumpers and Switches Slot Selection RSW1 Position Fpga Configuration Settings J1Fpga Configuration Settings J1 Location Function Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header Pinout Signal Direction Gpio Header P7Side View External Power Connector P8 External Power Connector Pinout P8 Signal DirectionConnector’s Mating Components and Cables Hardware Installation Heat Sink InstallationStand-alone Operation Software Installation Fpga Development EnvironmentPLX Software Development Kit SDK Reference Design & Application ExamplesFpga Configuration Power and Thermal Considerations Reference Design Fpga power analysisSpecifications Appendix a iMPACT Instructions for Fpga Configuration Launch ImpactPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga with the SPI Flash Configuring the Fpga / SPI flash AssociationPage Programming the Flash Elapsed time = Appendix B Power calculations Scenario 1 Heatsink attached, 250 LFMScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Reference Design Revision B Local Clock GenerationDDR2 Pinout Revision CConnector Pinouts Hardware DescriptionRevision B Revision C Specifications Revision B Revision C Power RequirementsRevision B
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