Connect Tech PCI-104 user manual Specifications, Revision B Revision C Power Requirements

Page 39

Connect Tech FreeForm/PCI-104 User Manual

External Power Connector (P8)

The connector no longer enables 3.3V regulation – i t is always enabled.

	Revision B
Pin	Signal

15V

23.3 enable (connect to 5V)

3GND

4VIO (connect to 5V)

	Revision C
Pin	Signal

15V

2

3GND

4VIO (connect to 5V)

Specifications

	Revision B		Revision C

Power Requirements	+3.3V DC and +5V DC, in PCI-104 stack	+5V	DC, in PCI-104 stack
	+5V DC stand-alone	+5V	DC stand-alone
	Current requirements are configuration
	dependant.

Revision 0.02

39

Image 39

Contents FreeForm/PCI-104 Limited Lifetime Warranty Copyright NoticeTrademark Acknowledgment Email/Internet Customer Support OverviewContact Information Telephone/FacsimileTable of Contents List of Figures List of TablesProduct Features IntroductionAbout this manual System Overview FreeForm/PCI-104 Block DiagramComponents Jumpers /Switches DescriptionReference Design Hardware Description Jumpers and SwitchesSlot Selection RSW1 Position Fpga Configuration Settings J1 Fpga Configuration Settings J1 Location FunctionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header P7 Gpio Header Pinout Signal DirectionExternal Power Connector Pinout P8 Signal Direction Side View External Power Connector P8Connector’s Mating Components and Cables Hardware Installation Heat Sink InstallationStand-alone Operation Reference Design & Application Examples Software InstallationFpga Development Environment PLX Software Development Kit SDKFpga Configuration Reference Design Fpga power analysis Power and Thermal ConsiderationsSpecifications Launch Impact Appendix a iMPACT Instructions for Fpga ConfigurationPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga / SPI flash Association Configuring the Fpga with the SPI FlashPage Programming the Flash Elapsed time = Scenario 1 Heatsink attached, 250 LFM Appendix B Power calculationsScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Revision C Reference DesignRevision B Local Clock Generation DDR2 PinoutConnector Pinouts Hardware DescriptionRevision B Revision C Specifications Revision B Revision C Power RequirementsRevision B