Connect Tech PCI-104 user manual Reference Design

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Connect Tech FreeForm/PCI-104 User Manual

Reference Design

The FreeForm/PCI-104 ships with a pre-installed reference design that is loaded into the FPGA’s configuration flash. This reference design demonstrates how to interface the FreeForm/PCI-104 (Virtex-5 FPGA) with the PLX PCI 9056 PCI to Local Bus Bridge, as well as the various peripherals.

The PLX 9056 provides a generic local bus that is capable of operating at up to 66MHz (this design forwards a 50MHz clock to the PLX). The PLX bridge has been set in the C-Mode of operation. The reference logic operates as a local bus slave, as well as a local bus master.

The reference design contains examples demonstrating:

oLoading of PLX 9056’s registers via the local bus o Local bus slave transfers

o Local bus master transfers o GPIO control

o Programming the SPI Flash

o Interfacing to the built-in Virtex-5 TEMACs o RS-485 serial data transfers

o Reading/writing to the serial EEPROM o Reading/writing to DDR2 memory

o Interfacing to the Virtex-5 Rocket I/O transceivers

Most of the example VHDL modules demonstrate how to interface with the various peripherals through a register set, which is accessible by the host system over the PCI bus. A set of software applications has been created to show how the host system can communicate with each FPGA sub-module. In most applications, the host system will not directly control these peripherals. In a custom application, these modules can be easily modified to interconnect with each other through the FPGA fabric.

To obtain the source code, refer to Software Installation. For further details on the reference design, refer to FreeForm/PCI-104 Reference Design Guide (CTIM-00042)

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Contents FreeForm/PCI-104 Limited Lifetime Warranty Copyright NoticeTrademark Acknowledgment Contact Information Customer Support OverviewTelephone/Facsimile Email/InternetTable of Contents List of Figures List of TablesProduct Features IntroductionAbout this manual System Overview FreeForm/PCI-104 Block DiagramComponents Jumpers /Switches DescriptionReference Design Slot Selection RSW1 Position Fpga Configuration Settings J1 Jumpers and SwitchesFpga Configuration Settings J1 Location Function Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header P7 Gpio Header Pinout Signal DirectionExternal Power Connector Pinout P8 Signal Direction Side View External Power Connector P8Connector’s Mating Components and Cables Hardware Installation Heat Sink InstallationStand-alone Operation Fpga Development Environment Software InstallationPLX Software Development Kit SDK Reference Design & Application ExamplesFpga Configuration Reference Design Fpga power analysis Power and Thermal ConsiderationsSpecifications Launch Impact Appendix a iMPACT Instructions for Fpga ConfigurationPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga / SPI flash Association Configuring the Fpga with the SPI FlashPage Programming the Flash Elapsed time = Scenario 1 Heatsink attached, 250 LFM Appendix B Power calculationsScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Revision B Local Clock Generation Reference DesignDDR2 Pinout Revision CConnector Pinouts Hardware DescriptionRevision B Revision C Specifications Revision B Revision C Power RequirementsRevision B