Connect Tech
Table of Contents |
|
Limited Lifetime Warranty | 2 |
Copyright Notice | 2 |
Trademark Acknowledgment | 2 |
Customer Support Overview | 3 |
Contact Information | 3 |
Table of Contents | 4 |
List of Tables | 5 |
List of Figures | 5 |
Introduction | 6 |
Product Features | 6 |
About this manual | 6 |
System Overview | 7 |
Reference Design | 9 |
Hardware Description | 10 |
Jumpers and Switches | 10 |
Slot Selection (RSW1) | 10 |
FPGA Configuration Settings (J1) | 10 |
Connector Pinouts | 11 |
11 | |
JTAG Programming Header (P2) | 11 |
SPI Flash Programming Header (P3) | 11 |
12 | |
13 | |
GPIO Header (P7) | 14 |
External Power Connector (P8) | 15 |
Connector’s Mating Components and Cables | 16 |
Hardware Installation | 17 |
Heat Sink Installation | 17 |
17 | |
Software Installation | 18 |
FPGA Development Environment | 18 |
PLX Software Development Kit (SDK) | 18 |
Reference Design & Application Examples | 18 |
FPGA Configuration | 19 |
Power and Thermal Considerations | 20 |
Reference Design FPGA power analysis | 20 |
Specifications | 21 |
Appendix A: iMPACT Instructions for FPGA Configuration | 22 |
Launch Impact | 22 |
Programming the FPGA | 25 |
Generating a PROM (MCS) File | 26 |
Configuring the FPGA with the SPI Flash | 29 |
Configuring the FPGA / SPI flash Association | 29 |
Programming the Flash | 31 |
Appendix B: Power calculations | 33 |
Scenario 1: Heatsink attached, 250 LFM | 33 |
Scenario 2: No Heatsink, 250 LFM | 34 |
Scenario 3: No heatsink, 0 LFM | 35 |
Appendix C: Hardware Changes from Revision B | 36 |
Reference Design | 37 |
Hardware Description | 38 |
Connector Pinouts | 38 |
Specifications | 39 |
Revision 0.02 | 4 |