Connect Tech PCI-104 user manual List of Tables, List of Figures

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Connect Tech FreeForm/PCI-104 User Manual

List of Tables

 

Table 1: FreeForm/PCI-104 Components

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Table 2: Slot Selection (RSW1)

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Table 3: FPGA Configuration Settings (J1)

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Table 4: JTAG Programming Header Pinout (P2)

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Table 5: SPI Flash Programming Header Pinout (P3)

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Table 6: High-Speed serial Connector Pinout (P4)

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Table 7: RS-485 Port 1 Pinout (P5)

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Table 8: RS-485 Port 2 Pinout (P6)

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Table 9: GPIO Header Pinout

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Table 10: External Power Connector Pinout (P8)

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Table 11: Connector Mate Listing

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List of Figures

 

Figure 1: FreeForm/PCI-104 Block Diagram

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Figure 2: FreeForm/PCI-104 Layout

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Figure 3: External Power Connection

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Revision 0.02

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Contents FreeForm/PCI-104 Trademark Acknowledgment Limited Lifetime WarrantyCopyright Notice Contact Information Customer Support OverviewTelephone/Facsimile Email/InternetTable of Contents List of Figures List of TablesAbout this manual Product FeaturesIntroduction System Overview FreeForm/PCI-104 Block DiagramComponents Jumpers /Switches DescriptionReference Design Slot Selection RSW1 Position Fpga Configuration Settings J1 Jumpers and SwitchesFpga Configuration Settings J1 Location Function Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header P7 Gpio Header Pinout Signal DirectionExternal Power Connector Pinout P8 Signal Direction Side View External Power Connector P8Connector’s Mating Components and Cables Stand-alone Operation Hardware InstallationHeat Sink Installation Fpga Development Environment Software InstallationPLX Software Development Kit SDK Reference Design & Application ExamplesFpga Configuration Reference Design Fpga power analysis Power and Thermal ConsiderationsSpecifications Launch Impact Appendix a iMPACT Instructions for Fpga ConfigurationPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga / SPI flash Association Configuring the Fpga with the SPI FlashPage Programming the Flash Elapsed time = Scenario 1 Heatsink attached, 250 LFM Appendix B Power calculationsScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Revision B Local Clock Generation Reference DesignDDR2 Pinout Revision CRevision B Revision C Connector PinoutsHardware Description Revision B SpecificationsRevision B Revision C Power Requirements
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