Connect Tech PCI-104 user manual Introduction, Product Features, About this manual

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Connect Tech FreeForm/PCI-104 User Manual

Introduction

Connect Tech’s FreeForm/PCI-104 features Xilinx’s V irtex-5 multi-platform FPGA offering users a flexible, reconfigurable computing platform that also takes advantage of the high bandwidth capabilities of the PCI bus while communicating with various I/O interfaces.

Product Features

oPCI-104 form factor – 32-Bit/33MHz

oXilinx multi-platform Virtex-5 FPGA with 3 million logic gates o 2MB Flash for FPGA configuration storage

o 8MB Flash for embedded code storage

o Designed for embedded processing using MicroBlaze™ o 100MHz input clock

o 128MB DDR2-400 memory

o 2 x 10/100 Ethernet with modular jacks o 2 x RS-485 serial interface

o High-speed serial connector 4 x Rocket I/O (GTP) channels o 64 single ended or 32 LVDS general purpose I/O

o External 5V power connection for programming and development o JTAG test and programming chain

o Industrial temperature range of -40°C to 85°C o Ships preconfigured with a reference design

About this manual

This manual will provide the user with the following information:

oSystem overview

oIntroduction to the reference design

oDescription of jumpers, switches, and connector pinouts o Hardware installation instructions

o Software installation instructions o FPGA configuration details

o Specifications

Revision 0.02

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Contents FreeForm/PCI-104 Limited Lifetime Warranty Copyright NoticeTrademark Acknowledgment Telephone/Facsimile Customer Support OverviewContact Information Email/InternetTable of Contents List of Tables List of FiguresProduct Features IntroductionAbout this manual FreeForm/PCI-104 Block Diagram System OverviewJumpers /Switches Description ComponentsReference Design Fpga Configuration Settings J1 Location Function Jumpers and SwitchesSlot Selection RSW1 Position Fpga Configuration Settings J1 Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header Pinout Signal Direction Gpio Header P7Side View External Power Connector P8 External Power Connector Pinout P8 Signal DirectionConnector’s Mating Components and Cables Hardware Installation Heat Sink InstallationStand-alone Operation PLX Software Development Kit SDK Software InstallationFpga Development Environment Reference Design & Application ExamplesFpga Configuration Power and Thermal Considerations Reference Design Fpga power analysisSpecifications Appendix a iMPACT Instructions for Fpga Configuration Launch ImpactPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga with the SPI Flash Configuring the Fpga / SPI flash AssociationPage Programming the Flash Elapsed time = Appendix B Power calculations Scenario 1 Heatsink attached, 250 LFMScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B DDR2 Pinout Reference DesignRevision B Local Clock Generation Revision CConnector Pinouts Hardware DescriptionRevision B Revision C Specifications Revision B Revision C Power RequirementsRevision B