Connect Tech PCI-104 Appendix a iMPACT Instructions for Fpga Configuration, Launch Impact

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Connect Tech FreeForm/PCI-104 User Manual

Appendix A: iMPACT Instructions for FPGA Configuration

To configure the FPGA via JTAG, connect the JTAG programming cable to P2 ensuring that all JTAG signals align correctly. It is important to note that P2 also has the TRST signal on pin 1, which is not part of Xilinx’s Parallel or USB programming cables.

Launch Impact

1) Open iMPACT, and select create a new project

2)Select configure devices using boundary scan. iMPACT will scan the JTAG chain, and identify three devices. The first device will be the FPGA.

Revision 0.02

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Contents FreeForm/PCI-104 Copyright Notice Limited Lifetime WarrantyTrademark Acknowledgment Telephone/Facsimile Customer Support OverviewContact Information Email/InternetTable of Contents List of Tables List of FiguresIntroduction Product FeaturesAbout this manual FreeForm/PCI-104 Block Diagram System OverviewJumpers /Switches Description ComponentsReference Design Fpga Configuration Settings J1 Location Function Jumpers and SwitchesSlot Selection RSW1 Position Fpga Configuration Settings J1 Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header Pinout Signal Direction Gpio Header P7Side View External Power Connector P8 External Power Connector Pinout P8 Signal DirectionConnector’s Mating Components and Cables Heat Sink Installation Hardware InstallationStand-alone Operation PLX Software Development Kit SDK Software InstallationFpga Development Environment Reference Design & Application ExamplesFpga Configuration Power and Thermal Considerations Reference Design Fpga power analysisSpecifications Appendix a iMPACT Instructions for Fpga Configuration Launch ImpactPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga with the SPI Flash Configuring the Fpga / SPI flash AssociationPage Programming the Flash Elapsed time = Appendix B Power calculations Scenario 1 Heatsink attached, 250 LFMScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B DDR2 Pinout Reference DesignRevision B Local Clock Generation Revision CHardware Description Connector PinoutsRevision B Revision C Revision B Revision C Power Requirements SpecificationsRevision B