Connect Tech PCI-104 user manual Software Installation, Fpga Development Environment

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Connect Tech FreeForm/PCI-104 User Manual

Software Installation

FPGA Development Environment

FreeForm/PCI-104 has been developed with Xilinx WebPACK 9.2, available free of charge at:

http://www.xilinx.com/ise/logic_design_prod/webpack.htm

PLX Software Development Kit (SDK)

PLX provides a software development kit (SDK) to aid in the creation of applications using the PLX 9056 bridge. The SDK provides a generic driver for Windows 2000/XP and Linux. A common API is also included; which encapsulates functions like:

oConfiguration register read / write

oBlock read / block write to local address space (i.e. memory / registers in the FPGA) o Physical memory allocation, for bus mastering or DMA purposes

o Interrupt handling

o EEPROM read/write by address

The SDK is available for download from:

http://www.plxtech.com/products/sdk/

In order to download the SDK, you will need to register with PLX.

Reference Design & Application Examples

The FreeForm/PCI-104 ships with a CD containing:

oDocumentation and manuals o FPGA VHDL reference design o Software program examples

The reference design and example programs help users quickly develop custom hardware and software applications. Refer to the CD for installation instructions.

The latest reference design is always available from:

http://devel.connecttech.com/

If a username and password have not already been provided, please contact Connect Tech Support via email support@connecttech.com.

Revision 0.02

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Contents FreeForm/PCI-104 Limited Lifetime Warranty Copyright NoticeTrademark Acknowledgment Telephone/Facsimile Customer Support OverviewContact Information Email/InternetTable of Contents List of Tables List of FiguresProduct Features IntroductionAbout this manual FreeForm/PCI-104 Block Diagram System OverviewJumpers /Switches Description ComponentsReference Design Fpga Configuration Settings J1 Location Function Jumpers and SwitchesSlot Selection RSW1 Position Fpga Configuration Settings J1 Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header Pinout Signal Direction Gpio Header P7Side View External Power Connector P8 External Power Connector Pinout P8 Signal DirectionConnector’s Mating Components and Cables Hardware Installation Heat Sink InstallationStand-alone Operation PLX Software Development Kit SDK Software InstallationFpga Development Environment Reference Design & Application ExamplesFpga Configuration Power and Thermal Considerations Reference Design Fpga power analysisSpecifications Appendix a iMPACT Instructions for Fpga Configuration Launch ImpactPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga with the SPI Flash Configuring the Fpga / SPI flash AssociationPage Programming the Flash Elapsed time = Appendix B Power calculations Scenario 1 Heatsink attached, 250 LFMScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B DDR2 Pinout Reference DesignRevision B Local Clock Generation Revision CConnector Pinouts Hardware DescriptionRevision B Revision C Specifications Revision B Revision C Power RequirementsRevision B