Connect Tech PCI-104 Power and Thermal Considerations, Reference Design Fpga power analysis

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Connect Tech FreeForm/PCI-104 User Manual

Power and Thermal Considerations

The FreeForm/PCI-104’s Virtex-5 FPGA is a versatile, flexible device, with many built-in features like termination, PLLs, and high speed gigabit transceivers. The drawback of these on-chip features is that they consume a lot of power and hence dissipate a lot of heat.

As a result Connect Tech, is recommending the installation of a heatsink, included with the product (see section Heat Sink Installation). As well, the FPGA designer must perform power analysis on their design to determine that they are not stressing the Virtex-5 component (i.e. exceeding the junction temperature).

Power analysis can be performed using the Xpower Analyzer (part of the ISE design suite) and the XPE spreadsheets (Xilinx Power Estimator Spreadsheets).

http://www.xilinx.com/products/design_resources/power_central/

Reference Design FPGA power analysis

Power analysis was performed on the FCG001 when configured with the reference design. The Virtex- 5 XPE spreadsheet was used to determine an effective junction to ambient thermal resistance (θJA_effective). The following parameters are entered into the spreadsheet to determine θJA_effective.

Device

 

Part

XC5VLX30T

Package

FF665

Grade

Industrial

Process

Typical

Speed Grade

-1

Stepping

Stepping - 1

 

 

Thermal Information

 

Ambient Temp (°C)

50

Airflow (LFM)

250

Heat Sink

Custom

Custom ΘSA (°C/W)

8 (*)

Board Selection

Small (4"x4")

# of Board Layers

12 to 15

(θSA is the surface to ambient temperature for a heatsink with dimensions 27 mm x 27 mm x 6.4 mm and 250 LFM airflow. The θSA improves (decreases) with a taller heatsink. )

Three scenarios were developed and the XPE parameters Airflow and Custom ΘSA were varied. The θJA_effective was entered into the Xpower Analyzer yielding a Juction Temperature @ 50 °C and a maximum ambient temperature. The following table summarizes the scenarios and the results. For complete details of the scenarios, see Appendix B.

Scenario

θJA_effective (°C/W)

Tambient_max

Tjunction at 50 °C

Heatsink attached, 250 LFM

4.9

82.7

67.3

No Heatsink, 250 LFM

6.4

72.7

72.7

No heatsink, 0 LFM

9.7

65.1

84.9

Calculation details:

Tjunction = Tambient + (PFPGA * θJA_effective) = 50°C + (3.53W * 4.9 °C /W) = 67.297°C

Tambient_max = Tjunction_max - (PFPGA * θJA_effective) = 100°C - (3.53W * 4.9 °C /W) = 82.7°C

Note Tjunction_absolute_max = 125°C is not used, since this is the absolute poi nt of failure.

Revision 0.02

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Contents FreeForm/PCI-104 Trademark Acknowledgment Limited Lifetime WarrantyCopyright Notice Customer Support Overview Contact InformationTelephone/Facsimile Email/InternetTable of Contents List of Tables List of FiguresAbout this manual Product FeaturesIntroduction FreeForm/PCI-104 Block Diagram System OverviewJumpers /Switches Description ComponentsReference Design Jumpers and Switches Slot Selection RSW1 Position Fpga Configuration Settings J1Fpga Configuration Settings J1 Location Function Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header Pinout Signal Direction Gpio Header P7Side View External Power Connector P8 External Power Connector Pinout P8 Signal DirectionConnector’s Mating Components and Cables Stand-alone Operation Hardware InstallationHeat Sink Installation Software Installation Fpga Development EnvironmentPLX Software Development Kit SDK Reference Design & Application ExamplesFpga Configuration Power and Thermal Considerations Reference Design Fpga power analysisSpecifications Appendix a iMPACT Instructions for Fpga Configuration Launch ImpactPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga with the SPI Flash Configuring the Fpga / SPI flash AssociationPage Programming the Flash Elapsed time = Appendix B Power calculations Scenario 1 Heatsink attached, 250 LFMScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Reference Design Revision B Local Clock GenerationDDR2 Pinout Revision CRevision B Revision C Connector PinoutsHardware Description Revision B SpecificationsRevision B Revision C Power Requirements