Connect Tech PCI-104 user manual MTGRXN0112

Page 12

Connect Tech FreeForm/PCI-104 User Manual

High-speed Serial (P4)

The high-speed serial connector carries four Rocket (GTP) I/O channels, each with a dedicated transmit and receive differential pair. These channels are capable of operating up 3.125 Gbps, depending on configuration. For more information on Rocket I/O capabilities, visit the Xilinx website: http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/

Table 6: High-Speed serial Connector Pinout (P4)

Pin

Signal

Direction

Notes

1

MTGRXN0_112

Input

(b)

3

MTGRXP0_112

Input

(b)

2

MTGTXN0_112

Output

(b)

4

MTGTXP0_112

Output

(b)

5

HSS_USER_IO(0)

Input/Output

(a), (d)

7

HSS_USER_IO(1)

Input/Output

(a), (d)

6

HSS_USER_IO(2)

Input/Output

(a), (d)

8

HSS_USER_IO(3)

Input/Output

(a), (d)

 

 

 

 

9

MTGRXN1_112

Input

(b)

11

MTGRXP1_112

Input

(b)

10

MTGTXN1_112

Output

(b)

12

MTGTXP1_112

Output

(b)

13

3.3V

Power

(a)

15

3.3V

Power

(a)

14

3.3V

Power

(a)

16

3.3V

Power

(a)

17

MTGRXN0_114

Input

(c)

19

MTGRXP0_114

Input

(c)

18

MTGTXN0_114

Output

(c)

20

MTGTXP0_114

Output

(c)

21

3.3V

Power

(a)

23

3.3V

Power

(a)

22

3.3V

Power

(a)

24

3.3V

Power

(a)

25

MTGRXN1_114

Input

(c)

27

MTGRXP1_114

Input

(c)

26

MTGTXN1_114

Output

(c)

28

MTGTXP1_114

Output

(c)

Notes:

a)Pins have a different function from Revision B.

b)The Rocket I/O (GTP) are organized into tiles, where each tile has two transceivers and shares a common PLL. In this design, tiles 112 and 114 are used.

c)Tile 112 has AC coupling capacitors on the TX pairs, validated at PCI Express data rates (2.5 Gbps).

d)Tile 114 has AC coupling capacitors on both the RX and TX pairs, validated at SATA data rates (1.5 Gbps).

e)HSS_USER_IO are flexible LVCMOS side-band signals.

WARNING If connecting two FreeForm/PCI-104’s together using the Rocket I/O interface in a cross-over fashion; care must be taken. Ensure that only cables provided by Connect Tech are used. Cables ordered directly from Samtec or a third party could result in damage to the cable and/or the FreeForm/PCI-104 board itself.

Revision 0.02

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Contents FreeForm/PCI-104 Limited Lifetime Warranty Copyright NoticeTrademark Acknowledgment Customer Support Overview Contact InformationTelephone/Facsimile Email/InternetTable of Contents List of Tables List of FiguresProduct Features IntroductionAbout this manual FreeForm/PCI-104 Block Diagram System OverviewJumpers /Switches Description ComponentsReference Design Jumpers and Switches Slot Selection RSW1 Position Fpga Configuration Settings J1Fpga Configuration Settings J1 Location Function Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header Pinout Signal Direction Gpio Header P7Side View External Power Connector P8 External Power Connector Pinout P8 Signal DirectionConnector’s Mating Components and Cables Hardware Installation Heat Sink InstallationStand-alone Operation Software Installation Fpga Development EnvironmentPLX Software Development Kit SDK Reference Design & Application ExamplesFpga Configuration Power and Thermal Considerations Reference Design Fpga power analysisSpecifications Appendix a iMPACT Instructions for Fpga Configuration Launch ImpactPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga with the SPI Flash Configuring the Fpga / SPI flash AssociationPage Programming the Flash Elapsed time = Appendix B Power calculations Scenario 1 Heatsink attached, 250 LFMScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Reference Design Revision B Local Clock GenerationDDR2 Pinout Revision CConnector Pinouts Hardware DescriptionRevision B Revision C Specifications Revision B Revision C Power RequirementsRevision B
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