Connect Tech PCI-104 user manual Elapsed time =

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Connect Tech FreeForm/PCI-104 User Manual

3)Observe the results in the transcript window.

a.The SPI core is first download to the FPGA device

b.The IDCODE is checked and verified

c.Flash is erased

d.Flash is programmed

After completion of the flash programming, the FPGA will attempt to configure itself from the flash. If the SPI flash setting is not selected with J1; this step will fail. This does not mean the flash is not programmed, but rather the verification of the programmed contents has failed.

'1': SPI access core not detected. SPI access core will be downloaded to the device to enable operations.

PROGRESS_START - Starting Operation. '1': Downloading core...

done.

'1': Reading status register contents...

INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 0011 1111 1001 1110 0000 1010 1000 0000 INFO:iMPACT:2492 - '1': Completed downloading core to device. INFO:iMPACT - '1': Checking done pin....done.

'1': Core downloaded successfully.

'1': IDCODE is '202015' (in hex).

'1': ID Check passed.

'1': IDCODE is '202015' (in hex). '1': ID Check passed.

'1': Erasing Device.

'1': Programming Device.

'1': Reading device contents...

done.

'1': Verification completed.

INFO:iMPACT - '1': Checking done pin....done.

'1': Programmed successfully.

INFO:iMPACT - '1': Checking done pin....done.

'1': Programmed successfully. PROGRESS_END - End Operation.

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Contents FreeForm/PCI-104 Trademark Acknowledgment Limited Lifetime WarrantyCopyright Notice Customer Support Overview Contact InformationTelephone/Facsimile Email/InternetTable of Contents List of Tables List of FiguresAbout this manual Product FeaturesIntroduction FreeForm/PCI-104 Block Diagram System OverviewJumpers /Switches Description ComponentsReference Design Jumpers and Switches Slot Selection RSW1 Position Fpga Configuration Settings J1Fpga Configuration Settings J1 Location Function Hardware DescriptionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header Pinout Signal Direction Gpio Header P7Side View External Power Connector P8 External Power Connector Pinout P8 Signal DirectionConnector’s Mating Components and Cables Stand-alone Operation Hardware InstallationHeat Sink Installation Software Installation Fpga Development EnvironmentPLX Software Development Kit SDK Reference Design & Application ExamplesFpga Configuration Power and Thermal Considerations Reference Design Fpga power analysisSpecifications Appendix a iMPACT Instructions for Fpga Configuration Launch ImpactPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga with the SPI Flash Configuring the Fpga / SPI flash AssociationPage Programming the Flash Elapsed time = Appendix B Power calculations Scenario 1 Heatsink attached, 250 LFMScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Reference Design Revision B Local Clock GenerationDDR2 Pinout Revision CRevision B Revision C Connector PinoutsHardware Description Revision B SpecificationsRevision B Revision C Power Requirements