Connect Tech PCI-104 user manual Fpga Configuration

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Connect Tech FreeForm/PCI-104 User Manual

FPGA Configuration

The Virtex-5 FPGA can be configured via two methods:

oJTAG programming chain, using P2

oSPI Flash, read on, power-up by FPGA

The configuration flash can be programmed (loaded) through three methods:

oJTAG programming chain (through FPGA), using P2 o Direct with cable, using P3

o Indirect programming through FPGA, only possible after configuration is complete (refer to reference design for more details)

To configure the FPGA via the JTAG / boundary scan programming chain, three items are required:

oFPGA bitstream (*.bit), generated at end FPGA implementation using ISE o PLX 9056 boundary scan definition file (*.bdsl)

o Ethernet PHY boundary scan definition file

To program the SPI flash, a hex file must be generated (*.mcs) then written to the flash. To generate the hex file, the following is required:

oFPGA Bitstream

oSetting PROM file format to MCS (important since bits are swapped) o Setting SPI PROM density to 16M

o Setting SPI Flash type to M25P16

For a complete procedure, refer to Appendix A.

Revision 0.02

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Contents FreeForm/PCI-104 Copyright Notice Limited Lifetime WarrantyTrademark Acknowledgment Email/Internet Customer Support OverviewContact Information Telephone/FacsimileTable of Contents List of Figures List of TablesIntroduction Product FeaturesAbout this manual System Overview FreeForm/PCI-104 Block DiagramComponents Jumpers /Switches DescriptionReference Design Hardware Description Jumpers and SwitchesSlot Selection RSW1 Position Fpga Configuration Settings J1 Fpga Configuration Settings J1 Location FunctionConnector Pinouts MTGRXN0112 RS-485 Port 2 Pinout P6 Signal Direction Gpio Header P7 Gpio Header Pinout Signal DirectionExternal Power Connector Pinout P8 Signal Direction Side View External Power Connector P8Connector’s Mating Components and Cables Heat Sink Installation Hardware InstallationStand-alone Operation Reference Design & Application Examples Software InstallationFpga Development Environment PLX Software Development Kit SDKFpga Configuration Reference Design Fpga power analysis Power and Thermal ConsiderationsSpecifications Launch Impact Appendix a iMPACT Instructions for Fpga ConfigurationPage Page Programming the Fpga Generating a Prom MCS File Page Revision Configuring the Fpga / SPI flash Association Configuring the Fpga with the SPI FlashPage Programming the Flash Elapsed time = Scenario 1 Heatsink attached, 250 LFM Appendix B Power calculationsScenario 2 No Heatsink, 250 LFM Scenario 3 No heatsink, 0 LFM Appendix C Hardware Changes from Revision B Revision C Reference DesignRevision B Local Clock Generation DDR2 PinoutHardware Description Connector PinoutsRevision B Revision C Revision B Revision C Power Requirements SpecificationsRevision B