Xilinx DS610 manual Device DNA Data Retention, Read Endurance, Symbol Description Minimum Units

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R

DC and Switching Characteristics

External Termination Requirements for Differential I/O

LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards

Bank 0 and 2

Bank 0

Bank 2

VCCO = 3.3V VCCO = 2.5V

LVDS_33, LVDS_25,

MINI_LVDS_33, MINI_LVDS_25,

RSDS_33, RSDS_25,

PPDS_33 PPDS_25

		Any Bank
			Bank 0
	1/4 th of Bourns	Bank 3	Bank1
Z0 = 50Ω	Part Number		Bank 2
Z0 = 50Ω	CAT16-PT4F4		Bank 2

Z0 = 50Ω					100Ω
Z0 = 50Ω

No VCCO Restrictions

LVDS_33, LVDS_25, MINI_LVDS_33, MINI_LVDS_25, RSDS_33, RSDS_25, PPDS_33, PPDS_25

DIFF_TERM=No

a) Input-only differential pairs or pairs not using DIFF_TERM=Yes constraint

Z0 = 50Ω

VCCO = 3.3V VCCO = 2.5V

VCCO = 3.3V

VCCO = 2.5V

LVDS_33,

LVDS_25,

MINI_LVDS_33,

MINI_LVDS_25,

Z0 = 50

Ω

RSDS_33,

RSDS_25,

PPDS_33

PPDS_25

RDT

LVDS_33, LVDS_25,

MINI_LVDS_33, MINI_LVDS_25,

RSDS_33, RSDS_25,

PPDS_33 PPDS_25

DIFF_TERM=Yes
b) Differential pairs using DIFF_TERM=Yes constraint	DS529-3_09_020107
	DS529-3_09_020107

Figure 5: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards

BLVDS_25 I/O Standard

Any Bank

Any Bank

	Bank 0		1/4 th of Bourns	1/4 th of Bourns			Bank 0
	3	B				3	B
	Bank	ank1				Bank	ank1
	Bank	ank1	Part Number	Part Number		Bank	ank1
	Bank 2		CAT16-LV4F12	CAT16-PT4F4			Bank 2
	VCCO = 2.5V		165Ω	Z0 = 50Ω	No VCCO Requirement
			165Ω

BLVDS_25	140Ω	Z0	= 50Ω	100Ω BLVDS_25
		Z0	= 50Ω

165Ω

DS529-3_07_020107

Figure 6: External Termination Resistors for BLVDS_25 I/O Standard

TMDS_33 I/O Standard

Bank 0 and 2

Bank 0

Bank 2

VCCO = 3.3V

		Any Bank
			Bank 0
	3.3V	3	B
	3.3V	Bank	ank 1
50Ω		Bank	ank 1
50Ω		50Ω	Bank 2
			Bank 2
		VCCAUX = 3.3V

TMDS_33

TMDS_33

DVI/HDMI cableDS529-3_08_020107

Figure 7: External Input Resistors Required for TMDS_33 I/O Standard

Device DNA Data Retention, Read Endurance

Table 14: Device DNA Identifier Memory Characteristics

Symbol		Description	Minimum	Units
DNA_RETENTION	Data retention, continuous usage		10	Years

DNA_CYCLES	Number of READ operations or JTAG ISC_DNA read operations. Unaffected by		30,000,000	Read
DNA_CYCLES	HOLD or SHIFT operations.		30,000,000	cycles
	HOLD or SHIFT operations.			cycles


DS610-3 (v2.0) July 16, 2007		www.xilinx.com		19
Product Specification

Image 19

Contents DS610-3 v2.0 July 16 Product SpecificationDS610-1 v2.0 July 16 DS610-2 v2.0 July 16Data Sheet Introduction FeaturesSpartan-3A and Spartan-3A DSP Fpga Differences Introduction and Ordering Information ConfigurationArchitectural Overview CapabilitiesXC3SD3400A DCMCS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A 519 227Pb-Free Packaging Package MarkingOrdering Information Standard PackagingDate Version Revision Revision HistoryIntroduction and Ordering Information DS610-2 v2.0 July 16 Added Low-power options no changes to this moduleFunctional Description Absolute Maximum Ratings DC Electrical CharacteristicsSymbol Description Conditions Min Max Units Absolute Maximum RatingsSymbol Description Min Max Units Power Supply SpecificationsDC and Switching Characteristics Supply Voltage Thresholds for Power-On ResetSymbol Description Test Conditions Min Typ Max Units General DC Characteristics for I/O Pins= GND Maximum2 Quiescent Supply Current CharacteristicsTypical2 Commercial Industrial Symbol Description Device Quiescent Current RequirementsCCO for Drivers Single-Ended I/O StandardsAttribute Min Nom Max Attribute Max Min Test Logic Level Conditions CharacteristicsAttribute Test Logic Level ConditionsIostandard Attribute CCO for Drivers Differential I/O StandardsMin Nom Max Min mV Nom mV Max mV Iostandard Attribute Min mV Typ mV Max mV External Termination Requirements for Differential I/O Device DNA Identifier Memory CharacteristicsSymbol Description Minimum Units Device DNA Data Retention, Read EnduranceSoftware Version Requirements Switching CharacteristicsSpartan-3A DSP Speed File Version History Sign Up for Alerts on Xilinx MySupportSpartan-3A DSP v1.29 Speed Grade Designations At the Output pin. The DCM is not Use TimingPin-to-Pin Clock-to-Output Times for the IOB Output Path Rate, without DCMHold Times Ifddelayvalue =Speed Grade Symbol Description ConditionsDevice Min Units Setup Times Set/Reset Pulse WidthIoplid Differential Standards Single-Ended StandardsLvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI333 PCI663Asynchronous Output Enable/Disable Times Set/Reset TimesTiming for the IOB Three-State Path QuietIO QuietIO 27.67QuietIO 24.97 QuietIO 25.92Inputs Only LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25Inputs Signal Standard Inputs OutputsTiming Measurement Methodology Test Methods for Timing Measurement at I/OsDifferential RT ΩVicm + Equivalent VCCO/GND Pairs per Bank Simultaneously Switching Output GuidelinesDevice CS484 FG676 XC3SD1800A XC3SD3400A Package Type Signal Standard Top, Bottom Left, RightCS484, FG676 Differential Standards Number of I/O Pairs or Channels QuietIO PCI333 PCI663CLB Slicem Timing Configurable Logic Block CLB TimingClock Timing CLB Shift Register Switching Characteristics Clock Buffer/Multiplexer Switching CharacteristicsClock Distribution Switching Characteristics Block RAM Timing Block RAM TimingClock Frequency DSP48A Timing Setup Times for the DSP48ASpeed Grade Symbol Description Setup Times of Data Pins to the Pipeline Register ClockMaximum Frequency Clock to Out from Pipeline Register Clock to Output PinsClock to Out from Input Register Clock to Output Pins Combinatorial Delays from Input Pins to Output PinsRecommended Operating Conditions for the DLL Delay-Locked Loop DLLInput Clock Jitter Tolerance Delay Path Variation4 Digital Clock Manager DCM TimingSpeed Grade Symbol Description Recommended Operating Conditions for the DFS Switching Characteristics for the DFSSpeed Grade Symbol Description Units Min Max Digital Frequency Synthesizer DFSMiscellaneous DCM Timing Phase Shifter PSSwitching Characteristics for the PS in Variable Phase Mode Phase Shifting RangeDnaport Interface Timing DNA Port TimingSymbol Description Min Typ Max Units Suspend Mode TimingEntering Suspend Mode Exiting Suspend Mode Entering Suspend ModeGeneral Configuration Power-On/Reconfigure Timing Configuration and Jtag TimingAll Speed Grades Symbol Description Device Min Max Units 11.2 Configuration Clock Cclk CharacteristicsMaster Mode Cclk Output Period by ConfigRate Option Setting Cclk clock period byCclk Low and High time Master Mode Cclk Output Minimum Low and High TimeSlave Mode Cclk Input Low and High Time Equivalent Cclk clock frequencySlave All Speed Grades Symbol Description Master Serial and Slave Serial Mode TimingMin Max Units Clock-to-Output Times Slave Parallel Mode Timing Symbol Description Minimum Serial Peripheral Interface SPI Configuration TimingSymbol Description Requirement Units Hold time on M20 mode pins after the rising edge of Initb Byte Peripheral Interface BPI Configuration TimingSymbol Description Minimum Maximum Units Setup time on M20 mode pins before the rising edge of InitbParallel NOR Flash Prom chip-select time Symbol Description Requirement UnitsParallel NOR Flash Prom output-enable time Parallel NOR Flash Prom read access timeINTEST, EXTEST, Sample Ieee 1149.1/1553 Jtag Test Access Port TimingDSP48A timing in and Table Diffhstli and Diffhstliii to , , and . Updated Tmds DCDC and Switching Characteristics Pin Types Types of Pins on Spartan-3A DSP FPGAsType/Color Description Pin Names in Type Code Maximum User I/O by Package Package Pins by TypePinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Power and Ground Supply Pins by PackageSpartan-3A DSP Package Thermal Characteristics Package Thermal CharacteristicsPinout Descriptions Bank Pin Name CS484 Type Ball CS484 484-Ball Chip-Scale Ball Grid ArrayPinout Table Spartan-3A DSP CS484 PinoutPinout Descriptions Spartan-3A DSP CS484 Pinout AA6 Input VCCO1AA3 Dual AA4AA1 Vref VCCO2 AA5 Vcco AA9VCCO2 VCCO2 VccoGND AA7 VCCO3 VccoGND AB1 Vccaux TMS Jtag TDO Vccaux Progb Config DoneVccaux TCK JtagUser I/Os Per Bank for the XC3SD3400A in the CS484 Package User I/Os by BankFootprint Migration Differences User I/Os Per Bank for the XC3SD1800A in the CS484 PackageLeft Half of Package top view CS484 FootprintRight Half of CS484 Package top view Spartan-3A DSP FG676 Pinout for XC3SD1800A Fpga FG676 676-Ball Fine-Pitch Ball Grid ArrayPinout Table Spartan-3A DSP FG676 Pinout forIOL26N0/GCLK7 IOL26P0/GCLK6IOL31P1/RHCLK2 IOL30N1/RHCLK1IOL30P1/RHCLK0 IOL33P1/RHCLK4IOL27P2/GCLK0 IOL17P2/RDWRBAF7 Input AF3AF4 AF5IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 Vref IP2/VREF2 AB6 VrefAB9 IOL30N2/MOSI/CSIBIOL35N3/LHCLK7 IOL33P3/LHCLK2IOL34N3/LHCLK5 IOL34P3/LHCLK4AD2 AE1 InputAE2 Vref AD1GND AA1 AA6 Vccaux Progb Config TDI Jtag TDOGND AF1 AF6 GND AD3 AD8519 314 User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the FG676 Package Top 128 RightFG676 Package Footprint for XC3SD1800A Fpga top view FG676 FootprintTDO IOL01P0 G20 Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaBank XC3SD3400A Pin Name FG676 Type Ball IOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0IP1/VREF1 VCCO0 Vcco IOL01P1/HDCIOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16 IOL34P1/IRDY1/RHCLK6T25 IOL05N1 AC25 IOL06P1IOL12P2 Y10 VCCO2 AF7 Vcco AE5 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22IOL36N3 IOL37P3 IOL53P3 IOL53N3 IP3IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IOL10N3 IOL03N3 IP3 IP3/VREF3 VrefAA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND GND AA1 AA4 AA6 GND AD3 AD5 AD8GND AC5 AC7 GND AB3Vccint AA8 Vccaux AF2 AB4 AB5Bottom 112 Left Vref are on Input pinsUser I/Os Per Bank for the XC3SD3400A in the FG676 Package Top 111 RightPinout Descriptions FG676 Package Footprint for XC3SD3400A Fpga top viewVCCO0 VREF1 VREF1 FG676 Footprint Migration DifferencesPinout Descriptions FG676 Footprint Migration Differences Migration RecommendationsFpga and XC3SD3400A Fpga . Minor edits SPARTAN-3A DSPPinout Descriptions