Xilinx DS610 manual Phase Shifter PS, Miscellaneous DCM Timing, Phase Shifting Range

DC and Switching Characteristics

R

Phase Shifter (PS)

Table 39: Recommended Operating Conditions for the PS in Variable Phase Mode

			Speed Grade
		-5			-4
Symbol	Description	Min	Max	Min		Max	Units
Operating Frequency Ranges
PSCLK_FREQ	Frequency for the PSCLK input	1	167	1		167	MHz
(FPSCLK)
Input Pulse Requirements
PSCLK_PULSE	PSCLK pulse width as a percentage of the PSCLK period	40%	60%	40%		60%	-

Table 40: Switching Characteristics for the PS in Variable Phase Mode

Symbol	Description		Phase Shift Amount	Units
Phase Shifting Range
MAX_STEPS(2)	Maximum allowed number of	CLKIN < 60 MHz	±[INTEGER(10 • (TCLKIN – 3 ns))]	steps
	DCM_DELAY_STEP steps for a given
		CLKIN ≥ 60 MHz	±[INTEGER(15 • (TCLKIN – 3 ns))]
	CLKIN clock period, where T = CLKIN
	clock period in ns. If using
	CLKIN_DIVIDE_BY_2 = TRUE,
	double the clock effective clock
	period.
FINE_SHIFT_RANGE_MIN	Minimum guaranteed delay for variable phase shifting		±[MAX_STEPS •	ns
			DCM_DELAY_STEP_MIN]
FINE_SHIFT_RANGE_MAX	Maximum guaranteed delay for variable phase shifting		±[MAX_STEPS •	ns
			DCM_DELAY_STEP_MAX]

Notes:

1.The numbers in this table are based on the operating conditions set forth in Table 7 and Table 39.

2.The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the PHASE_SHIFT attribute is set to 0.

3.The DCM_DELAY_STEP values are provided at the bottom of Table 36.

Miscellaneous DCM Timing

Table 41: Miscellaneous DCM Timing

Symbol	Description	Min	Max	Units
DCM_RST_PW_MIN	Minimum duration of a RST pulse width	3	-	CLKIN
				cycles

44	www.xilinx.com	DS610-3 (v2.0) July 16, 2007
		Product Specification