Xilinx DS610 manual IP3/VREF3 Vref, IOL10N3 IOL03N3 IP3, AA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND

Page 89

R

Pinout Descriptions

Table 65: Spartan-3A DSP FG676 Pinout for

XC3SD3400A FPGA (Continued)

Bank

XC3SD3400A Pin Name

FG676

Type

Ball

 

 

 

3

IO_L23N_3

K2

I/O

 

 

 

 

3

IO_L23P_3

K3

I/O

 

 

 

 

3

IO_L22N_3

K4

I/O

 

 

 

 

3

IO_L22P_3

K5

I/O

 

 

 

 

3

IO_L18P_3

K6

I/O

 

 

 

 

3

IO_L13P_3

K7

I/O

 

 

 

 

3

IO_L05N_3

K8

I/O

 

 

 

 

3

IO_L05P_3

K9

I/O

 

 

 

 

3

IP_L24P_3

J1

INPUT

 

 

 

 

3

IP_L20N_3/VREF_3

J2

VREF

 

 

 

 

3

IP_L20P_3

J3

INPUT

 

 

 

 

3

IO_L19N_3

J4

I/O

 

 

 

 

3

IO_L19P_3

J5

I/O

 

 

 

 

3

IO_L13N_3

J6

I/O

 

 

 

 

3

IO_L10P_3

J7

I/O

 

 

 

 

3

IO_L01P_3

J8

I/O

 

 

 

 

3

IO_L01N_3

J9

I/O

 

 

 

 

3

IO_L17N_3

H1

I/O

 

 

 

 

3

IO_L17P_3

H2

I/O

 

 

 

 

3

IP_3/VREF_3

H4

VREF

 

 

 

 

3

IO_L10N_3

H6

I/O

 

 

 

 

3

IO_L03N_3

H7

I/O

 

 

 

 

3

IP_3

G1

INPUT

 

 

 

 

3

IO_L14P_3

G3

I/O

 

 

 

 

3

IO_L09N_3

G4

I/O

 

 

 

 

3

IO_L03P_3

G6

I/O

 

 

 

 

3

IO_L11N_3

F2

I/O

 

 

 

 

3

IO_L14N_3

F3

I/O

 

 

 

 

3

IO_L07N_3

F4

I/O

 

 

 

 

3

IO_L09P_3

F5

I/O

 

 

 

 

3

IO_L11P_3

E1

I/O

 

 

 

 

3

IO_L07P_3

E3

I/O

 

 

 

 

3

IO_L06N_3

E4

I/O

 

 

 

 

3

IO_L06P_3

D3

I/O

 

 

 

 

3

IP_3/VREF_3

C1

VREF

 

 

 

 

3

IO_L02N_3

B1

I/O

 

 

 

 

3

IO_L02P_3

B2

I/O

 

 

 

 

3

IP_L66P_3

AE1

INPUT

 

 

 

 

3

IP_L66N_3/VREF_3

AE2

VREF

 

 

 

 

Table 65: Spartan-3A DSP FG676 Pinout for

XC3SD3400A FPGA (Continued)

Bank

XC3SD3400A Pin Name

FG676

Type

Ball

 

 

 

3

IO_L65P_3

AD1

I/O

 

 

 

 

3

IO_L65N_3

AD2

I/O

 

 

 

 

3

IO_L60N_3

AC1

I/O

 

 

 

 

3

IO_L64P_3

AC2

I/O

 

 

 

 

3

IO_L64N_3

AC3

I/O

 

 

 

 

3

IO_L60P_3

AB1

I/O

 

 

 

 

3

IO_L55P_3

AA2

I/O

 

 

 

 

3

IO_L55N_3

AA3

I/O

 

 

 

 

3

IP_3/VREF_3

AA5

VREF

 

 

 

 

3

VCCO_3

W5

VCCO

 

 

 

 

3

VCCO_3

T2

VCCO

 

 

 

 

3

VCCO_3

T8

VCCO

 

 

 

 

3

VCCO_3

P5

VCCO

 

 

 

 

3

VCCO_3

L2

VCCO

 

 

 

 

3

VCCO_3

L8

VCCO

 

 

 

 

3

VCCO_3

H5

VCCO

 

 

 

 

3

VCCO_3

E2

VCCO

 

 

 

 

3

VCCO_3

C2

VCCO

 

 

 

 

3

VCCO_3

AB2

VCCO

 

 

 

 

GND

GND

W8

GND

 

 

 

 

GND

GND

W14

GND

 

 

 

 

GND

GND

W19

GND

 

 

 

 

GND

GND

W24

GND

 

 

 

 

GND

GND

W25

GND

 

 

 

 

GND

GND

V3

GND

 

 

 

 

GND

GND

U10

GND

 

 

 

 

GND

GND

U13

GND

 

 

 

 

GND

GND

U17

GND

 

 

 

 

GND

GND

U25

GND

 

 

 

 

GND

GND

T1

GND

 

 

 

 

GND

GND

T6

GND

 

 

 

 

GND

GND

T12

GND

 

 

 

 

GND

GND

T14

GND

 

 

 

 

GND

GND

T16

GND

 

 

 

 

GND

GND

T21

GND

 

 

 

 

GND

GND

T26

GND

 

 

 

 

GND

GND

R11

GND

 

 

 

 

GND

GND

R13

GND

 

 

 

 

GND

GND

R15

GND

 

 

 

 

DS610-4 (v2.0) July 16, 2007

www.xilinx.com

89

Product Specification

Image 89
Contents DS610-1 v2.0 July 16 Product SpecificationDS610-2 v2.0 July 16 DS610-3 v2.0 July 16Data Sheet Spartan-3A and Spartan-3A DSP Fpga Differences FeaturesIntroduction Architectural Overview ConfigurationCapabilities Introduction and Ordering InformationCS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A DCM519 227 XC3SD3400AOrdering Information Package MarkingStandard Packaging Pb-Free PackagingDate Version Revision Revision HistoryIntroduction and Ordering Information DS610-2 v2.0 July 16 Added Low-power options no changes to this moduleFunctional Description Symbol Description Conditions Min Max Units DC Electrical CharacteristicsAbsolute Maximum Ratings Absolute Maximum RatingsDC and Switching Characteristics Power Supply SpecificationsSupply Voltage Thresholds for Power-On Reset Symbol Description Min Max Units= GND General DC Characteristics for I/O PinsSymbol Description Test Conditions Min Typ Max Units Typical2 Commercial Industrial Symbol Description Device Quiescent Supply Current CharacteristicsQuiescent Current Requirements Maximum2Attribute Min Nom Max Single-Ended I/O StandardsCCO for Drivers Attribute Test Logic Level Conditions CharacteristicsTest Logic Level Conditions Attribute Max MinMin Nom Max Min mV Nom mV Max mV Differential I/O StandardsIostandard Attribute CCO for Drivers Iostandard Attribute Min mV Typ mV Max mV Symbol Description Minimum Units Device DNA Identifier Memory CharacteristicsDevice DNA Data Retention, Read Endurance External Termination Requirements for Differential I/OSoftware Version Requirements Switching CharacteristicsSpartan-3A DSP v1.29 Speed Grade Designations Sign Up for Alerts on Xilinx MySupportSpartan-3A DSP Speed File Version History Pin-to-Pin Clock-to-Output Times for the IOB Output Path TimingRate, without DCM At the Output pin. The DCM is not UseHold Times Ifddelayvalue =Device Min Units Setup Times Symbol Description ConditionsSet/Reset Pulse Width Speed GradeIoplid Lvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 Single-Ended StandardsPCI333 PCI663 Differential StandardsTiming for the IOB Three-State Path Set/Reset TimesAsynchronous Output Enable/Disable Times QuietIO QuietIO 27.67QuietIO 24.97 QuietIO 25.92Inputs Only LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25Timing Measurement Methodology Signal Standard Inputs OutputsTest Methods for Timing Measurement at I/Os InputsVicm + RT ΩDifferential Device CS484 FG676 XC3SD1800A XC3SD3400A Simultaneously Switching Output GuidelinesEquivalent VCCO/GND Pairs per Bank CS484, FG676 Signal Standard Top, Bottom Left, RightPackage Type Differential Standards Number of I/O Pairs or Channels QuietIO PCI333 PCI663Clock Timing Configurable Logic Block CLB TimingCLB Slicem Timing Clock Distribution Switching Characteristics Clock Buffer/Multiplexer Switching CharacteristicsCLB Shift Register Switching Characteristics Clock Frequency Block RAM TimingBlock RAM Timing Speed Grade Symbol Description Setup Times for the DSP48ASetup Times of Data Pins to the Pipeline Register Clock DSP48A TimingClock to Out from Input Register Clock to Output Pins Clock to Out from Pipeline Register Clock to Output PinsCombinatorial Delays from Input Pins to Output Pins Maximum FrequencyInput Clock Jitter Tolerance Delay Path Variation4 Delay-Locked Loop DLLDigital Clock Manager DCM Timing Recommended Operating Conditions for the DLLSpeed Grade Symbol Description Speed Grade Symbol Description Units Min Max Switching Characteristics for the DFSDigital Frequency Synthesizer DFS Recommended Operating Conditions for the DFSSwitching Characteristics for the PS in Variable Phase Mode Phase Shifter PSPhase Shifting Range Miscellaneous DCM TimingDnaport Interface Timing DNA Port TimingEntering Suspend Mode Exiting Suspend Mode Suspend Mode TimingEntering Suspend Mode Symbol Description Min Typ Max UnitsAll Speed Grades Symbol Description Device Min Max Units Configuration and Jtag TimingGeneral Configuration Power-On/Reconfigure Timing Master Mode Cclk Output Period by ConfigRate Option Setting Configuration Clock Cclk CharacteristicsCclk clock period by 11.2Slave Mode Cclk Input Low and High Time Master Mode Cclk Output Minimum Low and High TimeEquivalent Cclk clock frequency Cclk Low and High timeMin Max Units Clock-to-Output Times Master Serial and Slave Serial Mode TimingSlave All Speed Grades Symbol Description Slave Parallel Mode Timing Symbol Description Minimum Serial Peripheral Interface SPI Configuration TimingSymbol Description Requirement Units Symbol Description Minimum Maximum Units Byte Peripheral Interface BPI Configuration TimingSetup time on M20 mode pins before the rising edge of Initb Hold time on M20 mode pins after the rising edge of InitbParallel NOR Flash Prom output-enable time Symbol Description Requirement UnitsParallel NOR Flash Prom read access time Parallel NOR Flash Prom chip-select timeINTEST, EXTEST, Sample Ieee 1149.1/1553 Jtag Test Access Port TimingDSP48A timing in and Table Diffhstli and Diffhstliii to , , and . Updated Tmds DCDC and Switching Characteristics Type/Color Description Pin Names in Type Code Types of Pins on Spartan-3A DSP FPGAsPin Types Pinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Package Pins by TypePower and Ground Supply Pins by Package Maximum User I/O by PackagePinout Descriptions Package Thermal CharacteristicsSpartan-3A DSP Package Thermal Characteristics Pinout Table CS484 484-Ball Chip-Scale Ball Grid ArraySpartan-3A DSP CS484 Pinout Bank Pin Name CS484 Type BallPinout Descriptions Spartan-3A DSP CS484 Pinout AA3 Dual VCCO1AA4 AA6 InputVCCO2 VCCO2 AA5 Vcco AA9VCCO2 Vcco AA1 VrefGND AB1 VCCO3 VccoGND AA7 Vccaux TCK Vccaux Progb Config DoneJtag Vccaux TMS Jtag TDOFootprint Migration Differences User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the CS484 Package User I/Os Per Bank for the XC3SD3400A in the CS484 PackageLeft Half of Package top view CS484 FootprintRight Half of CS484 Package top view Pinout Table FG676 676-Ball Fine-Pitch Ball Grid ArraySpartan-3A DSP FG676 Pinout for Spartan-3A DSP FG676 Pinout for XC3SD1800A FpgaIOL26N0/GCLK7 IOL26P0/GCLK6IOL30P1/RHCLK0 IOL30N1/RHCLK1IOL33P1/RHCLK4 IOL31P1/RHCLK2IOL27P2/GCLK0 IOL17P2/RDWRBAF4 AF3AF5 AF7 InputAB9 IP2/VREF2 AB6 VrefIOL30N2/MOSI/CSIB IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 VrefIOL34N3/LHCLK5 IOL33P3/LHCLK2IOL34P3/LHCLK4 IOL35N3/LHCLK7AE2 Vref AE1 InputAD1 AD2GND AF1 AF6 Vccaux Progb Config TDI Jtag TDOGND AD3 AD8 GND AA1 AA6User I/Os Per Bank for the XC3SD1800A in the FG676 Package User I/Os by BankTop 128 Right 519 314FG676 Package Footprint for XC3SD1800A Fpga top view FG676 FootprintTDO Bank XC3SD3400A Pin Name FG676 Type Ball Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaIOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 IOL01P0 G20IP1/VREF1 VCCO0 Vcco IOL01P1/HDCIOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16 IOL34P1/IRDY1/RHCLK6IOL12P2 Y10 IOL05N1 AC25 IOL06P1T25 IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 VCCO2 AF7 Vcco AE5IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IOL53P3 IOL53N3 IP3IOL36N3 IOL37P3 AA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND IP3/VREF3 VrefIOL10N3 IOL03N3 IP3 GND AC5 AC7 GND AD3 AD5 AD8GND AB3 GND AA1 AA4 AA6Vccint AA8 Vccaux AF2 AB4 AB5User I/Os Per Bank for the XC3SD3400A in the FG676 Package Vref are on Input pinsTop 111 Right Bottom 112 LeftPinout Descriptions FG676 Package Footprint for XC3SD3400A Fpga top viewVCCO0 VREF1 VREF1 FG676 Footprint Migration DifferencesPinout Descriptions FG676 Footprint Migration Differences Migration RecommendationsFpga and XC3SD3400A Fpga . Minor edits SPARTAN-3A DSPPinout Descriptions