Xilinx DS610 Migration Recommendations, Pinout Descriptions FG676 Footprint Migration Differences

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Pinout Descriptions

Table 67: FG676 Footprint Migration Differences (Continued)

R

	Spartan-3A		Spartan-3A DSP		Spartan-3A DSP

FG676	XC3S1400A	XC3S1400A	XC3SD1800A	XC3SD1800A	XC3SD3400A	XC3SD3400A	FG676
Ball	Type	Bank	Type	Bank	Type	Bank	Ball
Y8	N.C.	N.C.	IP_2	2	VCCINT	VCCINT	Y8

Y11	IP_2	2	IP_2	2	VCCINT	VCCINT	Y11

Y18	N.C.	N.C.	IP_2	2	VCCINT	VCCINT	Y18

Y19	N.C.	N.C.	IP_2/VREF_2	2	VCCINT	VCCINT	Y19

W18	N.C.	N.C.	IP_2	2	VCCINT	VCCINT	W18

AF2	IP_2	2	IP_2	2	VCCAUX	VCCAUX	AF2

AF7	IP_2	2	IP_2	2	VCCO_2	2	AF7

AD5	N.C.	N.C.	IP_2	2	GND	GND	AD5

AD23	N.C.	N.C.	IP_2	2	GND	GND	AD23

AC5	N.C.	N.C.	IP_2	2	GND	GND	AC5

AC7	IP_2	2	IP_2	2	GND	GND	AC7

AC18	IP_2	2	IP_2	2	GND	GND	AC18

AB10	IP_2/VREF_2	2	IP_2/VREF_2	2	GND	GND	AB10

AB17	IP_2	2	IP_2	2	VCCAUX	VCCAUX	AB17

AB20	IP_2	2	IP_2	2	GND	GND	AB20

AA8	N.C.	N.C.	IP_2	2	VCCINT	VCCINT	AA8

AA19	IP_2	2	IP_2	2	GND	GND	AA19

AC22	N.C.	N.C.	IO_2	2	IO_2	2	AC22

Y3	IP_L54P_3	3	IP_L54P_3	3	IP_3	3	Y3

Y4	IP_L54N_3	3	IP_L54N_3	3	VCCINT	VCCINT	Y4

H4	IP_L12N_3/	3	IP_L12N_3/	3	IP_3/VREF_3	3	H4
	VREF_3		VREF_3

G1	IP_L16N_3	3	IP_L16N_3	3	IP_3	3	G1

G2	IP_L16P_3	3	IP_L16P_3	3	GND	GND	G2

G5	IP_L12P_3	3	IP_L12P_3	3	GND	GND	G5

D1	IP_L08N_3	3	IP_L08N_3	3	VCCAUX	VCCAUX	D1

D2	IP_L08P_3	3	IP_L08P_3	3	GND	GND	D2

C1	IP_L04N_3/	3	IP_L04N_3/	3	IP_3/VREF_3	3	C1
	VREF_3		VREF_3

C2	IP_L04P_3	3	IP_L04P_3	3	VCCO_3	3	C2

AB3	IP_L62P_3	3	IP_L62P_3	3	GND	GND	AB3

AB4	IP_L62N_3	3	IP_L62N_3	3	VCCAUX	VCCAUX	AB4

AA4	IP_L58P_3	3	IP_L58P_3	3	GND	GND	AA4

AA5	IP_L58N_3/	3	IP_L58N_3/	3	IP_3/VREF_3	3	AA5
	VREF_3		VREF_3

Migration Recommendations

There are multiple pinout differences between the XC3SD1800A and the XC3SD3400A FPGAs in the FG676 package. Please note the differences between the two devices from Table 67 and take the necessary precautions.

96	www.xilinx.com	DS610-4 (v2.0) July 16, 2007
		Product Specification

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Contents Product Specification DS610-1 v2.0 July 16DS610-2 v2.0 July 16 DS610-3 v2.0 July 16Data Sheet Features IntroductionSpartan-3A and Spartan-3A DSP Fpga Differences Configuration Architectural OverviewCapabilities Introduction and Ordering InformationDCM CS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A519 227 XC3SD3400APackage Marking Ordering InformationStandard Packaging Pb-Free PackagingRevision History Date Version RevisionIntroduction and Ordering Information Added Low-power options no changes to this module DS610-2 v2.0 July 16Functional Description DC Electrical Characteristics Symbol Description Conditions Min Max UnitsAbsolute Maximum Ratings Absolute Maximum RatingsPower Supply Specifications DC and Switching CharacteristicsSupply Voltage Thresholds for Power-On Reset Symbol Description Min Max UnitsGeneral DC Characteristics for I/O Pins Symbol Description Test Conditions Min Typ Max Units= GND Quiescent Supply Current Characteristics Typical2 Commercial Industrial Symbol Description DeviceQuiescent Current Requirements Maximum2Single-Ended I/O Standards CCO for DriversAttribute Min Nom Max Test Logic Level Conditions Characteristics AttributeTest Logic Level Conditions Attribute Max MinDifferential I/O Standards Iostandard Attribute CCO for DriversMin Nom Max Min mV Nom mV Max mV Iostandard Attribute Min mV Typ mV Max mV Device DNA Identifier Memory Characteristics Symbol Description Minimum UnitsDevice DNA Data Retention, Read Endurance External Termination Requirements for Differential I/OSwitching Characteristics Software Version RequirementsSign Up for Alerts on Xilinx MySupport Spartan-3A DSP Speed File Version HistorySpartan-3A DSP v1.29 Speed Grade Designations Timing Pin-to-Pin Clock-to-Output Times for the IOB Output PathRate, without DCM At the Output pin. The DCM is not UseIfddelayvalue = Hold TimesSymbol Description Conditions Device Min Units Setup TimesSet/Reset Pulse Width Speed GradeIoplid Single-Ended Standards Lvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12PCI333 PCI663 Differential StandardsSet/Reset Times Asynchronous Output Enable/Disable TimesTiming for the IOB Three-State Path QuietIO 27.67 QuietIOQuietIO 25.92 QuietIO 24.97LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25 Inputs OnlySignal Standard Inputs Outputs Timing Measurement MethodologyTest Methods for Timing Measurement at I/Os InputsRT Ω DifferentialVicm + Simultaneously Switching Output Guidelines Equivalent VCCO/GND Pairs per BankDevice CS484 FG676 XC3SD1800A XC3SD3400A Signal Standard Top, Bottom Left, Right Package TypeCS484, FG676 QuietIO PCI333 PCI663 Differential Standards Number of I/O Pairs or ChannelsConfigurable Logic Block CLB Timing CLB Slicem TimingClock Timing Clock Buffer/Multiplexer Switching Characteristics CLB Shift Register Switching CharacteristicsClock Distribution Switching Characteristics Block RAM Timing Block RAM TimingClock Frequency Setup Times for the DSP48A Speed Grade Symbol DescriptionSetup Times of Data Pins to the Pipeline Register Clock DSP48A TimingClock to Out from Pipeline Register Clock to Output Pins Clock to Out from Input Register Clock to Output PinsCombinatorial Delays from Input Pins to Output Pins Maximum FrequencyDelay-Locked Loop DLL Input Clock Jitter Tolerance Delay Path Variation4Digital Clock Manager DCM Timing Recommended Operating Conditions for the DLLSpeed Grade Symbol Description Switching Characteristics for the DFS Speed Grade Symbol Description Units Min MaxDigital Frequency Synthesizer DFS Recommended Operating Conditions for the DFSPhase Shifter PS Switching Characteristics for the PS in Variable Phase ModePhase Shifting Range Miscellaneous DCM TimingDNA Port Timing Dnaport Interface TimingSuspend Mode Timing Entering Suspend Mode Exiting Suspend ModeEntering Suspend Mode Symbol Description Min Typ Max UnitsConfiguration and Jtag Timing General Configuration Power-On/Reconfigure TimingAll Speed Grades Symbol Description Device Min Max Units Configuration Clock Cclk Characteristics Master Mode Cclk Output Period by ConfigRate Option SettingCclk clock period by 11.2Master Mode Cclk Output Minimum Low and High Time Slave Mode Cclk Input Low and High TimeEquivalent Cclk clock frequency Cclk Low and High timeMaster Serial and Slave Serial Mode Timing Slave All Speed Grades Symbol DescriptionMin Max Units Clock-to-Output Times Slave Parallel Mode Timing Serial Peripheral Interface SPI Configuration Timing Symbol Description MinimumSymbol Description Requirement Units Byte Peripheral Interface BPI Configuration Timing Symbol Description Minimum Maximum UnitsSetup time on M20 mode pins before the rising edge of Initb Hold time on M20 mode pins after the rising edge of InitbSymbol Description Requirement Units Parallel NOR Flash Prom output-enable timeParallel NOR Flash Prom read access time Parallel NOR Flash Prom chip-select timeIeee 1149.1/1553 Jtag Test Access Port Timing INTEST, EXTEST, SampleDiffhstli and Diffhstliii to , , and . Updated Tmds DC DSP48A timing in and TableDC and Switching Characteristics Types of Pins on Spartan-3A DSP FPGAs Pin TypesType/Color Description Pin Names in Type Code Package Pins by Type Pinout Descriptions Types of Pins on Spartan-3A DSP FPGAsPower and Ground Supply Pins by Package Maximum User I/O by PackagePackage Thermal Characteristics Spartan-3A DSP Package Thermal CharacteristicsPinout Descriptions CS484 484-Ball Chip-Scale Ball Grid Array Pinout TableSpartan-3A DSP CS484 Pinout Bank Pin Name CS484 Type BallPinout Descriptions Spartan-3A DSP CS484 Pinout VCCO1 AA3 DualAA4 AA6 InputVCCO2 AA5 Vcco AA9 VCCO2VCCO2 Vcco AA1 VrefVCCO3 Vcco GND AA7GND AB1 Vccaux Progb Config Done Vccaux TCKJtag Vccaux TMS Jtag TDOUser I/Os by Bank Footprint Migration DifferencesUser I/Os Per Bank for the XC3SD1800A in the CS484 Package User I/Os Per Bank for the XC3SD3400A in the CS484 PackageCS484 Footprint Left Half of Package top viewRight Half of CS484 Package top view FG676 676-Ball Fine-Pitch Ball Grid Array Pinout TableSpartan-3A DSP FG676 Pinout for Spartan-3A DSP FG676 Pinout for XC3SD1800A FpgaIOL26P0/GCLK6 IOL26N0/GCLK7IOL30N1/RHCLK1 IOL30P1/RHCLK0IOL33P1/RHCLK4 IOL31P1/RHCLK2IOL17P2/RDWRB IOL27P2/GCLK0AF3 AF4AF5 AF7 InputIP2/VREF2 AB6 Vref AB9IOL30N2/MOSI/CSIB IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 VrefIOL33P3/LHCLK2 IOL34N3/LHCLK5IOL34P3/LHCLK4 IOL35N3/LHCLK7AE1 Input AE2 VrefAD1 AD2Vccaux Progb Config TDI Jtag TDO GND AF1 AF6GND AD3 AD8 GND AA1 AA6User I/Os by Bank User I/Os Per Bank for the XC3SD1800A in the FG676 PackageTop 128 Right 519 314FG676 Footprint FG676 Package Footprint for XC3SD1800A Fpga top viewTDO Spartan-3A DSP FG676 Pinout for XC3SD3400A Fpga Bank XC3SD3400A Pin Name FG676 Type BallIOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 IOL01P0 G20VCCO0 Vcco IOL01P1/HDC IP1/VREF1IOL34P1/IRDY1/RHCLK6 IOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16IOL05N1 AC25 IOL06P1 T25IOL12P2 Y10 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13 IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 VCCO2 AF7 Vcco AE5IOL53P3 IOL53N3 IP3 IOL36N3 IOL37P3IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IP3/VREF3 Vref IOL10N3 IOL03N3 IP3AA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND GND AD3 AD5 AD8 GND AC5 AC7GND AB3 GND AA1 AA4 AA6Vccaux AF2 AB4 AB5 Vccint AA8Vref are on Input pins User I/Os Per Bank for the XC3SD3400A in the FG676 PackageTop 111 Right Bottom 112 LeftFG676 Package Footprint for XC3SD3400A Fpga top view Pinout DescriptionsVCCO0 VREF1 FG676 Footprint Migration Differences VREF1Migration Recommendations Pinout Descriptions FG676 Footprint Migration DifferencesSPARTAN-3A DSP Fpga and XC3SD3400A Fpga . Minor editsPinout Descriptions