Xilinx DS610 manual Simultaneously Switching Output Guidelines, Equivalent VCCO/GND Pairs per Bank

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DC and Switching Characteristics

Using IBIS Models to Simulate Load Conditions in Application

IBIS models permit the most accurate prediction of timing delays for a given application. The parameters found in the

IBIS model (VREF, RREF, and VMEAS) correspond directly with the parameters used in Table 25 (VT, RT, and VM). Do

not confuse VREF (the termination voltage) from the IBIS model with VREF (the input-switching threshold) from the table. A fourth parameter, CREF, is always zero. The four parameters describe all relevant output test conditions. IBIS models are found in the Xilinx development software as well as at the following link:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

Delays for a given application are simulated according to its specific load conditions as follows:

1.Simulate the desired signal standard with the output driver connected to the test setup shown in Figure 8.

Use parameter values VT, RT, and VM from Table 25. CREF is zero.

2.Record the time to VM.

3.Simulate the same signal standard with the output driver connected to the PCB trace with load. Use the

appropriate IBIS model (including VREF, RREF, CREF, and VMEAS values) or capacitive value to represent the load.

4.Record the time to VMEAS.

5.Compare the results of steps 2 and 4. Add (or subtract) the increase (or decrease) in delay to (or from) the appropriate Output standard adjustment (Table 24) to yield the worst-case delay of the PCB trace.

Simultaneously Switching Output Guidelines

This section provides guidelines for the recommended maximum allowable number of Simultaneous Switching Outputs (SSOs). These guidelines describe the maximum number of user I/O pins of a given output signal standard that should simultaneously switch in the same direction, while maintaining a safe level of switching noise. Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce.

Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. The output drive transistors all conduct current to a common voltage rail. Low-to-High transitions conduct to the VCCO rail; High-to-Low transitions conduct to the GND rail. The resulting cumulative current transient induces a voltage difference across the inductance that exists between the die pad and the power supply or ground return. The inductance is associated with bonding wires, the package lead frame, and any other signal routing inside the package. Other variables contribute to SSO noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage consequently affects internal switching noise margins and ultimately signal quality.

Table 26 and Table 27 provide the essential SSO guidelines. For each device/package combination, Table 26 provides the number of equivalent VCCO/GND pairs. For each output signal standard and drive strength, Table 27 recommends the maximum number of SSOs, switching in the same direction, allowed per VCCO/GND pair within an I/O bank. The guidelines in Table 27 are categorized by package style, slew rate, and output drive current. Furthermore, the number of SSOs is specified by I/O bank.

Generally, the left and right I/O banks (Banks 1 and 3) support higher output drive current.

Multiply the appropriate numbers from Table 26 and Table 27 to calculate the maximum number of SSOs allowed within an I/O bank. Exceeding these SSO guidelines might result in increased power or ground bounce, degraded signal integrity, or increased system jitter.

SSOMAX/IO Bank = Table 26 x Table 27

The recommended maximum SSO values assumes that the FPGA is soldered on the printed circuit board and that the board uses sound design practices. The SSO values do not apply for FPGAs mounted in sockets, due to the lead inductance introduced by the socket.

Table 26: Equivalent VCCO/GND Pairs per Bank

 

Package Style (including Pb-free)

 

 

 

Device

CS484

FG676

XC3SD1800A

6

9

 

 

 

XC3SD3400A

6

10

 

 

 

DS610-3 (v2.0) July 16, 2007

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Product Specification

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Contents DS610-1 v2.0 July 16 Product SpecificationDS610-2 v2.0 July 16 DS610-3 v2.0 July 16Data Sheet Features IntroductionSpartan-3A and Spartan-3A DSP Fpga Differences Architectural Overview ConfigurationCapabilities Introduction and Ordering InformationCS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A DCM519 227 XC3SD3400AOrdering Information Package MarkingStandard Packaging Pb-Free PackagingDate Version Revision Revision HistoryIntroduction and Ordering Information DS610-2 v2.0 July 16 Added Low-power options no changes to this moduleFunctional Description Symbol Description Conditions Min Max Units DC Electrical CharacteristicsAbsolute Maximum Ratings Absolute Maximum RatingsDC and Switching Characteristics Power Supply SpecificationsSupply Voltage Thresholds for Power-On Reset Symbol Description Min Max UnitsGeneral DC Characteristics for I/O Pins Symbol Description Test Conditions Min Typ Max Units= GND Typical2 Commercial Industrial Symbol Description Device Quiescent Supply Current CharacteristicsQuiescent Current Requirements Maximum2Single-Ended I/O Standards CCO for DriversAttribute Min Nom Max Attribute Test Logic Level Conditions CharacteristicsTest Logic Level Conditions Attribute Max MinDifferential I/O Standards Iostandard Attribute CCO for DriversMin Nom Max Min mV Nom mV Max mV Iostandard Attribute Min mV Typ mV Max mV Symbol Description Minimum Units Device DNA Identifier Memory CharacteristicsDevice DNA Data Retention, Read Endurance External Termination Requirements for Differential I/OSoftware Version Requirements Switching CharacteristicsSign Up for Alerts on Xilinx MySupport Spartan-3A DSP Speed File Version HistorySpartan-3A DSP v1.29 Speed Grade Designations Pin-to-Pin Clock-to-Output Times for the IOB Output Path TimingRate, without DCM At the Output pin. The DCM is not UseHold Times Ifddelayvalue =Device Min Units Setup Times Symbol Description ConditionsSet/Reset Pulse Width Speed GradeIoplid Lvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 Single-Ended StandardsPCI333 PCI663 Differential StandardsSet/Reset Times Asynchronous Output Enable/Disable TimesTiming for the IOB Three-State Path QuietIO QuietIO 27.67QuietIO 24.97 QuietIO 25.92Inputs Only LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25Timing Measurement Methodology Signal Standard Inputs OutputsTest Methods for Timing Measurement at I/Os InputsRT Ω DifferentialVicm + Simultaneously Switching Output Guidelines Equivalent VCCO/GND Pairs per BankDevice CS484 FG676 XC3SD1800A XC3SD3400A Signal Standard Top, Bottom Left, Right Package TypeCS484, FG676 Differential Standards Number of I/O Pairs or Channels QuietIO PCI333 PCI663Configurable Logic Block CLB Timing CLB Slicem TimingClock Timing Clock Buffer/Multiplexer Switching Characteristics CLB Shift Register Switching CharacteristicsClock Distribution Switching Characteristics Block RAM Timing Block RAM TimingClock Frequency Speed Grade Symbol Description Setup Times for the DSP48ASetup Times of Data Pins to the Pipeline Register Clock DSP48A TimingClock to Out from Input Register Clock to Output Pins Clock to Out from Pipeline Register Clock to Output PinsCombinatorial Delays from Input Pins to Output Pins Maximum FrequencyInput Clock Jitter Tolerance Delay Path Variation4 Delay-Locked Loop DLLDigital Clock Manager DCM Timing Recommended Operating Conditions for the DLLSpeed Grade Symbol Description Speed Grade Symbol Description Units Min Max Switching Characteristics for the DFSDigital Frequency Synthesizer DFS Recommended Operating Conditions for the DFSSwitching Characteristics for the PS in Variable Phase Mode Phase Shifter PSPhase Shifting Range Miscellaneous DCM TimingDnaport Interface Timing DNA Port TimingEntering Suspend Mode Exiting Suspend Mode Suspend Mode TimingEntering Suspend Mode Symbol Description Min Typ Max UnitsConfiguration and Jtag Timing General Configuration Power-On/Reconfigure TimingAll Speed Grades Symbol Description Device Min Max Units Master Mode Cclk Output Period by ConfigRate Option Setting Configuration Clock Cclk CharacteristicsCclk clock period by 11.2Slave Mode Cclk Input Low and High Time Master Mode Cclk Output Minimum Low and High TimeEquivalent Cclk clock frequency Cclk Low and High timeMaster Serial and Slave Serial Mode Timing Slave All Speed Grades Symbol DescriptionMin Max Units Clock-to-Output Times Slave Parallel Mode Timing Symbol Description Minimum Serial Peripheral Interface SPI Configuration TimingSymbol Description Requirement Units Symbol Description Minimum Maximum Units Byte Peripheral Interface BPI Configuration TimingSetup time on M20 mode pins before the rising edge of Initb Hold time on M20 mode pins after the rising edge of InitbParallel NOR Flash Prom output-enable time Symbol Description Requirement UnitsParallel NOR Flash Prom read access time Parallel NOR Flash Prom chip-select timeINTEST, EXTEST, Sample Ieee 1149.1/1553 Jtag Test Access Port TimingDSP48A timing in and Table Diffhstli and Diffhstliii to , , and . Updated Tmds DCDC and Switching Characteristics Types of Pins on Spartan-3A DSP FPGAs Pin TypesType/Color Description Pin Names in Type Code Pinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Package Pins by TypePower and Ground Supply Pins by Package Maximum User I/O by PackagePackage Thermal Characteristics Spartan-3A DSP Package Thermal CharacteristicsPinout Descriptions Pinout Table CS484 484-Ball Chip-Scale Ball Grid ArraySpartan-3A DSP CS484 Pinout Bank Pin Name CS484 Type BallPinout Descriptions Spartan-3A DSP CS484 Pinout AA3 Dual VCCO1AA4 AA6 InputVCCO2 VCCO2 AA5 Vcco AA9VCCO2 Vcco AA1 VrefVCCO3 Vcco GND AA7GND AB1 Vccaux TCK Vccaux Progb Config DoneJtag Vccaux TMS Jtag TDOFootprint Migration Differences User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the CS484 Package User I/Os Per Bank for the XC3SD3400A in the CS484 PackageLeft Half of Package top view CS484 FootprintRight Half of CS484 Package top view Pinout Table FG676 676-Ball Fine-Pitch Ball Grid ArraySpartan-3A DSP FG676 Pinout for Spartan-3A DSP FG676 Pinout for XC3SD1800A FpgaIOL26N0/GCLK7 IOL26P0/GCLK6IOL30P1/RHCLK0 IOL30N1/RHCLK1IOL33P1/RHCLK4 IOL31P1/RHCLK2IOL27P2/GCLK0 IOL17P2/RDWRBAF4 AF3AF5 AF7 InputAB9 IP2/VREF2 AB6 VrefIOL30N2/MOSI/CSIB IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 VrefIOL34N3/LHCLK5 IOL33P3/LHCLK2IOL34P3/LHCLK4 IOL35N3/LHCLK7AE2 Vref AE1 InputAD1 AD2GND AF1 AF6 Vccaux Progb Config TDI Jtag TDOGND AD3 AD8 GND AA1 AA6User I/Os Per Bank for the XC3SD1800A in the FG676 Package User I/Os by BankTop 128 Right 519 314FG676 Package Footprint for XC3SD1800A Fpga top view FG676 FootprintTDO Bank XC3SD3400A Pin Name FG676 Type Ball Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaIOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 IOL01P0 G20IP1/VREF1 VCCO0 Vcco IOL01P1/HDCIOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16 IOL34P1/IRDY1/RHCLK6IOL05N1 AC25 IOL06P1 T25IOL12P2 Y10 IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 VCCO2 AF7 Vcco AE5IOL53P3 IOL53N3 IP3 IOL36N3 IOL37P3IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IP3/VREF3 Vref IOL10N3 IOL03N3 IP3AA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND GND AC5 AC7 GND AD3 AD5 AD8GND AB3 GND AA1 AA4 AA6Vccint AA8 Vccaux AF2 AB4 AB5User I/Os Per Bank for the XC3SD3400A in the FG676 Package Vref are on Input pinsTop 111 Right Bottom 112 LeftPinout Descriptions FG676 Package Footprint for XC3SD3400A Fpga top viewVCCO0 VREF1 VREF1 FG676 Footprint Migration DifferencesPinout Descriptions FG676 Footprint Migration Differences Migration RecommendationsFpga and XC3SD3400A Fpga . Minor edits SPARTAN-3A DSPPinout Descriptions
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