Xilinx DS610 manual Speed Grade Symbol Description

Page 42

DC and Switching Characteristics

Table 36: Switching Characteristics for the DLL

R

 

 

 

 

 

 

 

Speed Grade

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-5

 

-4

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Description

 

Device

Min

 

Max

Min

 

Max

Units

Output Frequency Ranges

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT_FREQ_CLK0

Frequency for the CLK0 and CLK180 outputs

 

All

5

 

280

5

 

250

MHz

 

 

 

 

 

 

 

 

 

 

 

CLKOUT_FREQ_CLK90

Frequency for the CLK90 and CLK270 outputs

 

 

5

 

200

5

 

200

MHz

 

 

 

 

 

 

 

 

 

 

 

CLKOUT_FREQ_2X

Frequency for the CLK2X and CLK2X180 outputs

 

 

10

 

334

10

 

334

MHz

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT_FREQ_DV

Frequency for the CLKDV output

 

 

 

0.3125

 

186

0.3125

 

166

MHz

 

 

 

 

 

 

 

 

 

 

 

 

Output Clock Jitter(2,3,4)

 

 

 

 

 

 

 

 

 

 

 

CLKOUT_PER_JITT_0

Period jitter at the CLK0 output

 

 

All

-

 

±100

-

 

±100

ps

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT_PER_JITT_90

Period jitter at the CLK90 output

 

 

 

-

 

±150

-

 

±150

ps

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT_PER_JITT_180

Period jitter at the CLK180 output

 

 

 

-

 

±150

-

 

±150

ps

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT_PER_JITT_270

Period jitter at the CLK270 output

 

 

 

-

 

±150

-

 

±150

ps

 

 

 

 

 

 

 

 

 

 

 

CLKOUT_PER_JITT_2X

Period jitter at the CLK2X and CLK2X180 outputs

 

 

-

 

±[0.5%

-

 

±[0.5%

ps

 

 

 

 

 

 

 

of CLKIN

 

 

of CLKIN

 

 

 

 

 

 

 

 

period

 

 

period

 

 

 

 

 

 

 

 

+ 100]

 

 

+ 100]

 

CLKOUT_PER_JITT_DV1

Period jitter at the CLKDV output when performing integer

 

-

 

±150

-

 

±150

ps

 

division

 

 

 

 

 

 

 

 

 

 

CLKOUT_PER_JITT_DV2

Period jitter at the CLKDV output when performing non-integer

 

-

 

±[0.5%

-

 

±[0.5%

ps

 

division

 

 

 

 

 

of CLKIN

 

 

of CLKIN

 

 

 

 

 

 

 

 

period

 

 

period

 

 

 

 

 

 

 

 

+ 100]

 

 

+ 100]

 

Duty Cycle(4)

 

 

 

 

 

 

 

 

 

 

 

CLKOUT_DUTY_CYCLE_DLL

Duty cycle variation for the CLK0, CLK90, CLK180, CLK270,

All

-

 

±[1% of

-

 

±[1% of

ps

 

CLK2X, CLK2X180, and CLKDV outputs, including the

 

 

 

CLKIN

 

 

CLKIN

 

 

BUFGMUX and clock tree duty-cycle distortion

 

 

 

 

period

 

 

period

 

 

 

 

 

 

 

 

+ 350]

 

 

+ 350]

 

Phase Alignment(4)

 

 

 

 

 

 

 

 

 

 

 

CLKIN_CLKFB_PHASE

Phase offset between the CLKIN and CLKFB inputs

 

All

-

 

±150

-

 

±150

ps

 

 

 

 

 

 

 

 

 

 

 

CLKOUT_PHASE_DLL

Phase offset between DLL outputs

CLK0 to CLK2X

 

-

 

±[1% of

-

 

±[1% of

ps

 

 

(not CLK2X180)

 

 

 

CLKIN

 

 

CLKIN

 

 

 

 

 

 

 

 

period

 

 

period

 

 

 

 

 

 

 

 

+ 100]

 

 

+ 100]

 

 

 

All others

 

-

 

±[1% of

-

 

±[1% of

ps

 

 

 

 

 

 

 

CLKIN

 

 

CLKIN

 

 

 

 

 

 

 

 

period

 

 

period

 

 

 

 

 

 

 

 

+ 150]

 

 

+ 150]

 

Lock Time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOCK_DLL(3)

When using the DLL alone: The

5 MHz < F

< 15 MHz

All

-

 

5

-

 

5

ms

 

time from deassertion at the DCM’s

CLKIN

 

 

 

 

 

 

 

 

 

 

FCLKIN > 15 MHz

 

-

 

600

-

 

600

μs

 

Reset input to the rising transition

 

 

 

 

at its LOCKED output. When the

 

 

 

 

 

 

 

 

 

 

 

DCM is locked, the CLKIN and

 

 

 

 

 

 

 

 

 

 

 

CLKFB signals are in phase

 

 

 

 

 

 

 

 

 

 

Delay Lines

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DCM_DELAY_STEP(5)

Finest delay resolution, averaged over all steps

 

All

15

 

35

15

 

35

ps

Notes:

1.The numbers in this table are based on the operating conditions set forth in Table 7 and Table 35.

2.Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.

3.For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.

4.Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter of “±[1%

of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250 ps, averaged over all steps.

5.The typical delay step size is 23 ps.

42

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DS610-3 (v2.0) July 16, 2007

 

 

Product Specification

Image 42
Contents DS610-2 v2.0 July 16 Product SpecificationDS610-1 v2.0 July 16 DS610-3 v2.0 July 16Data Sheet Features IntroductionSpartan-3A and Spartan-3A DSP Fpga Differences Capabilities ConfigurationArchitectural Overview Introduction and Ordering Information519 227 DCMCS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A XC3SD3400AStandard Packaging Package MarkingOrdering Information Pb-Free PackagingRevision History Date Version RevisionIntroduction and Ordering Information Added Low-power options no changes to this module DS610-2 v2.0 July 16Functional Description Absolute Maximum Ratings DC Electrical CharacteristicsSymbol Description Conditions Min Max Units Absolute Maximum RatingsSupply Voltage Thresholds for Power-On Reset Power Supply SpecificationsDC and Switching Characteristics Symbol Description Min Max UnitsGeneral DC Characteristics for I/O Pins Symbol Description Test Conditions Min Typ Max Units= GND Quiescent Current Requirements Quiescent Supply Current CharacteristicsTypical2 Commercial Industrial Symbol Description Device Maximum2Single-Ended I/O Standards CCO for DriversAttribute Min Nom Max Test Logic Level Conditions Test Logic Level Conditions CharacteristicsAttribute Attribute Max MinDifferential I/O Standards Iostandard Attribute CCO for DriversMin Nom Max Min mV Nom mV Max mV Iostandard Attribute Min mV Typ mV Max mV Device DNA Data Retention, Read Endurance Device DNA Identifier Memory CharacteristicsSymbol Description Minimum Units External Termination Requirements for Differential I/OSwitching Characteristics Software Version RequirementsSign Up for Alerts on Xilinx MySupport Spartan-3A DSP Speed File Version HistorySpartan-3A DSP v1.29 Speed Grade Designations Rate, without DCM TimingPin-to-Pin Clock-to-Output Times for the IOB Output Path At the Output pin. The DCM is not UseIfddelayvalue = Hold TimesSet/Reset Pulse Width Symbol Description ConditionsDevice Min Units Setup Times Speed GradeIoplid PCI333 PCI663 Single-Ended StandardsLvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 Differential StandardsSet/Reset Times Asynchronous Output Enable/Disable TimesTiming for the IOB Three-State Path QuietIO 27.67 QuietIOQuietIO 25.92 QuietIO 24.97LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25 Inputs OnlyTest Methods for Timing Measurement at I/Os Signal Standard Inputs OutputsTiming Measurement Methodology InputsRT Ω DifferentialVicm + Simultaneously Switching Output Guidelines Equivalent VCCO/GND Pairs per BankDevice CS484 FG676 XC3SD1800A XC3SD3400A Signal Standard Top, Bottom Left, Right Package TypeCS484, FG676 QuietIO PCI333 PCI663 Differential Standards Number of I/O Pairs or ChannelsConfigurable Logic Block CLB Timing CLB Slicem TimingClock Timing Clock Buffer/Multiplexer Switching Characteristics CLB Shift Register Switching CharacteristicsClock Distribution Switching Characteristics Block RAM Timing Block RAM TimingClock Frequency Setup Times of Data Pins to the Pipeline Register Clock Setup Times for the DSP48ASpeed Grade Symbol Description DSP48A TimingCombinatorial Delays from Input Pins to Output Pins Clock to Out from Pipeline Register Clock to Output PinsClock to Out from Input Register Clock to Output Pins Maximum FrequencyDigital Clock Manager DCM Timing Delay-Locked Loop DLLInput Clock Jitter Tolerance Delay Path Variation4 Recommended Operating Conditions for the DLLSpeed Grade Symbol Description Digital Frequency Synthesizer DFS Switching Characteristics for the DFSSpeed Grade Symbol Description Units Min Max Recommended Operating Conditions for the DFSPhase Shifting Range Phase Shifter PSSwitching Characteristics for the PS in Variable Phase Mode Miscellaneous DCM TimingDNA Port Timing Dnaport Interface TimingEntering Suspend Mode Suspend Mode TimingEntering Suspend Mode Exiting Suspend Mode Symbol Description Min Typ Max UnitsConfiguration and Jtag Timing General Configuration Power-On/Reconfigure TimingAll Speed Grades Symbol Description Device Min Max Units Cclk clock period by Configuration Clock Cclk CharacteristicsMaster Mode Cclk Output Period by ConfigRate Option Setting 11.2Equivalent Cclk clock frequency Master Mode Cclk Output Minimum Low and High TimeSlave Mode Cclk Input Low and High Time Cclk Low and High timeMaster Serial and Slave Serial Mode Timing Slave All Speed Grades Symbol DescriptionMin Max Units Clock-to-Output Times Slave Parallel Mode Timing Serial Peripheral Interface SPI Configuration Timing Symbol Description MinimumSymbol Description Requirement Units Setup time on M20 mode pins before the rising edge of Initb Byte Peripheral Interface BPI Configuration TimingSymbol Description Minimum Maximum Units Hold time on M20 mode pins after the rising edge of InitbParallel NOR Flash Prom read access time Symbol Description Requirement UnitsParallel NOR Flash Prom output-enable time Parallel NOR Flash Prom chip-select timeIeee 1149.1/1553 Jtag Test Access Port Timing INTEST, EXTEST, SampleDiffhstli and Diffhstliii to , , and . Updated Tmds DC DSP48A timing in and TableDC and Switching Characteristics Types of Pins on Spartan-3A DSP FPGAs Pin TypesType/Color Description Pin Names in Type Code Power and Ground Supply Pins by Package Package Pins by TypePinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Maximum User I/O by PackagePackage Thermal Characteristics Spartan-3A DSP Package Thermal CharacteristicsPinout Descriptions Spartan-3A DSP CS484 Pinout CS484 484-Ball Chip-Scale Ball Grid ArrayPinout Table Bank Pin Name CS484 Type BallPinout Descriptions Spartan-3A DSP CS484 Pinout AA4 VCCO1AA3 Dual AA6 InputVCCO2 Vcco VCCO2 AA5 Vcco AA9VCCO2 AA1 VrefVCCO3 Vcco GND AA7GND AB1 Jtag Vccaux Progb Config DoneVccaux TCK Vccaux TMS Jtag TDOUser I/Os Per Bank for the XC3SD1800A in the CS484 Package User I/Os by BankFootprint Migration Differences User I/Os Per Bank for the XC3SD3400A in the CS484 PackageCS484 Footprint Left Half of Package top viewRight Half of CS484 Package top view Spartan-3A DSP FG676 Pinout for FG676 676-Ball Fine-Pitch Ball Grid ArrayPinout Table Spartan-3A DSP FG676 Pinout for XC3SD1800A FpgaIOL26P0/GCLK6 IOL26N0/GCLK7IOL33P1/RHCLK4 IOL30N1/RHCLK1IOL30P1/RHCLK0 IOL31P1/RHCLK2IOL17P2/RDWRB IOL27P2/GCLK0AF5 AF3AF4 AF7 InputIOL30N2/MOSI/CSIB IP2/VREF2 AB6 VrefAB9 IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 VrefIOL34P3/LHCLK4 IOL33P3/LHCLK2IOL34N3/LHCLK5 IOL35N3/LHCLK7AD1 AE1 InputAE2 Vref AD2GND AD3 AD8 Vccaux Progb Config TDI Jtag TDOGND AF1 AF6 GND AA1 AA6Top 128 Right User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the FG676 Package 519 314FG676 Footprint FG676 Package Footprint for XC3SD1800A Fpga top viewTDO IOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaBank XC3SD3400A Pin Name FG676 Type Ball IOL01P0 G20VCCO0 Vcco IOL01P1/HDC IP1/VREF1IOL34P1/IRDY1/RHCLK6 IOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16IOL05N1 AC25 IOL06P1 T25IOL12P2 Y10 IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 VCCO2 AF7 Vcco AE5IOL53P3 IOL53N3 IP3 IOL36N3 IOL37P3IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IP3/VREF3 Vref IOL10N3 IOL03N3 IP3AA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND GND AB3 GND AD3 AD5 AD8GND AC5 AC7 GND AA1 AA4 AA6Vccaux AF2 AB4 AB5 Vccint AA8Top 111 Right Vref are on Input pinsUser I/Os Per Bank for the XC3SD3400A in the FG676 Package Bottom 112 LeftFG676 Package Footprint for XC3SD3400A Fpga top view Pinout DescriptionsVCCO0 VREF1 FG676 Footprint Migration Differences VREF1Migration Recommendations Pinout Descriptions FG676 Footprint Migration DifferencesSPARTAN-3A DSP Fpga and XC3SD3400A Fpga . Minor editsPinout Descriptions