Xilinx manual IOL34P1/IRDY1/RHCLK6, IOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16

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R

Pinout Descriptions

Table 65: Spartan-3A DSP FG676 Pinout for

XC3SD3400A FPGA (Continued)

	Bank	XC3SD3400A Pin Name	FG676	Type
	Bank	XC3SD3400A Pin Name	Ball	Type
			Ball
	1	IO_L12N_1	U18	I/O

	1	IO_L12P_1	U19	I/O

	1	IO_L10N_1	U20	I/O

	1	IO_L14P_1	U21	I/O

	1	IO_L21N_1	U22	I/O

	1	IO_L23P_1	U23	I/O

	1	IO_L23N_1/VREF_1	U24	VREF

	1	IP_1/VREF_1	U26	VREF

	1	IO_L17N_1	T17	I/O

	1	IO_L17P_1	T18	I/O

	1	IO_L14N_1	T20	I/O

	1	IO_L26P_1/A4	T23	DUAL

	1	IO_L26N_1/A5	T24	DUAL

	1	IO_L27N_1/A7	R17	DUAL

	1	IO_L27P_1/A6	R18	DUAL

	1	IO_L22P_1	R19	I/O

	1	IO_L22N_1	R20	I/O

	1	IO_L25P_1/A2	R21	DUAL

	1	IO_L25N_1/A3	R22	DUAL

	1	IP_L28P_1/VREF_1	R23	VREF

	1	IP_L28N_1	R24	INPUT

	1	IO_L29P_1/A8	R25	DUAL

	1	IO_L29N_1/A9	R26	DUAL

	1	IO_L34P_1/IRDY1/RHCLK6	P18	RHCLK

	1	IO_L30N_1/RHCLK1	P20	RHCLK

	1	IO_L30P_1/RHCLK0	P21	RHCLK

	1	IO_L37P_1	P22	I/O

	1	IO_L33P_1/RHCLK4	P23	RHCLK

	1	IO_L31N_1/TRDY1/RHCLK3	P25	RHCLK

	1	IO_L31P_1/RHCLK2	P26	RHCLK

	1	IO_L39N_1/A15	N17	DUAL

	1	IO_L39P_1/A14	N18	DUAL

	1	IO_L34N_1/RHCLK7	N19	RHCLK

	1	IO_L42P_1/A16	N20	DUAL

	1	IO_L37N_1	N21	I/O

	1	IP_L36N_1	N23	INPUT

	1	IO_L33N_1/RHCLK5	N24	RHCLK

	1	IP_L32N_1	N25	INPUT

	1	IP_L32P_1	N26	INPUT

Table 65: Spartan-3A DSP FG676 Pinout for

XC3SD3400A FPGA (Continued)

	Bank	XC3SD3400A Pin Name	FG676	Type
	Bank	XC3SD3400A Pin Name	Ball	Type
			Ball
	1	IO_L47N_1	M18	I/O

	1	IO_L47P_1	M19	I/O

	1	IO_L42N_1/A17	M20	DUAL

	1	IO_L45P_1	M21	I/O

	1	IO_L45N_1	M22	I/O

	1	IO_L38N_1/A13	M23	DUAL

	1	IP_L36P_1/VREF_1	M24	VREF

	1	IO_L35N_1/A11	M25	DUAL

	1	IO_L35P_1/A10	M26	DUAL

	1	IO_L55N_1	L17	I/O

	1	IO_L55P_1	L18	I/O

	1	IO_L53P_1	L20	I/O

	1	IO_L50P_1	L22	I/O

	1	IP_L40N_1	L23	INPUT

	1	IO_L38P_1/A12	L24	DUAL

	1	IO_L57N_1	K18	I/O

	1	IO_L57P_1	K19	I/O

	1	IO_L53N_1	K20	I/O

	1	IO_L50N_1	K21	I/O

	1	IO_L46N_1	K22	I/O

	1	IO_L46P_1	K23	I/O

	1	IP_L40P_1	K24	INPUT

	1	IO_L41P_1	K25	I/O

	1	IO_L41N_1	K26	I/O

	1	IO_L59P_1	J19	I/O

	1	IO_L59N_1	J20	I/O

	1	IO_L62P_1/A20	J21	DUAL

	1	IO_L49N_1	J22	I/O

	1	IO_L49P_1	J23	I/O

	1	IO_L43N_1/A19	J25	DUAL

	1	IO_L43P_1/A18	J26	DUAL

	1	IO_L64P_1/A24	H20	DUAL

	1	IO_L62N_1/A21	H21	DUAL

	1	IP_1	H24	INPUT

	1	IP_1/VREF_1	H26	VREF

	1	IO_L64N_1/A25	G21	DUAL

	1	IO_L58N_1	G22	I/O

	1	IO_L51P_1	G23	I/O

	1	IO_L51N_1	G24	I/O

DS610-4 (v2.0) July 16, 2007

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Product Specification

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Contents DS610-1 v2.0 July 16 Product SpecificationDS610-2 v2.0 July 16 DS610-3 v2.0 July 16Data Sheet Introduction FeaturesSpartan-3A and Spartan-3A DSP Fpga Differences Architectural Overview ConfigurationCapabilities Introduction and Ordering InformationCS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A DCM519 227 XC3SD3400AOrdering Information Package MarkingStandard Packaging Pb-Free PackagingDate Version Revision Revision HistoryIntroduction and Ordering Information DS610-2 v2.0 July 16 Added Low-power options no changes to this moduleFunctional Description Symbol Description Conditions Min Max Units DC Electrical CharacteristicsAbsolute Maximum Ratings Absolute Maximum RatingsDC and Switching Characteristics Power Supply SpecificationsSupply Voltage Thresholds for Power-On Reset Symbol Description Min Max UnitsSymbol Description Test Conditions Min Typ Max Units General DC Characteristics for I/O Pins= GND Typical2 Commercial Industrial Symbol Description Device Quiescent Supply Current CharacteristicsQuiescent Current Requirements Maximum2CCO for Drivers Single-Ended I/O StandardsAttribute Min Nom Max Attribute Test Logic Level Conditions CharacteristicsTest Logic Level Conditions Attribute Max MinIostandard Attribute CCO for Drivers Differential I/O StandardsMin Nom Max Min mV Nom mV Max mV Iostandard Attribute Min mV Typ mV Max mV Symbol Description Minimum Units Device DNA Identifier Memory CharacteristicsDevice DNA Data Retention, Read Endurance External Termination Requirements for Differential I/OSoftware Version Requirements Switching CharacteristicsSpartan-3A DSP Speed File Version History Sign Up for Alerts on Xilinx MySupportSpartan-3A DSP v1.29 Speed Grade Designations Pin-to-Pin Clock-to-Output Times for the IOB Output Path TimingRate, without DCM At the Output pin. The DCM is not UseHold Times Ifddelayvalue =Device Min Units Setup Times Symbol Description ConditionsSet/Reset Pulse Width Speed GradeIoplid Lvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 Single-Ended StandardsPCI333 PCI663 Differential StandardsAsynchronous Output Enable/Disable Times Set/Reset TimesTiming for the IOB Three-State Path QuietIO QuietIO 27.67QuietIO 24.97 QuietIO 25.92Inputs Only LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25Timing Measurement Methodology Signal Standard Inputs OutputsTest Methods for Timing Measurement at I/Os InputsDifferential RT ΩVicm + Equivalent VCCO/GND Pairs per Bank Simultaneously Switching Output GuidelinesDevice CS484 FG676 XC3SD1800A XC3SD3400A Package Type Signal Standard Top, Bottom Left, RightCS484, FG676 Differential Standards Number of I/O Pairs or Channels QuietIO PCI333 PCI663CLB Slicem Timing Configurable Logic Block CLB TimingClock Timing CLB Shift Register Switching Characteristics Clock Buffer/Multiplexer Switching CharacteristicsClock Distribution Switching Characteristics Block RAM Timing Block RAM TimingClock Frequency Speed Grade Symbol Description Setup Times for the DSP48ASetup Times of Data Pins to the Pipeline Register Clock DSP48A TimingClock to Out from Input Register Clock to Output Pins Clock to Out from Pipeline Register Clock to Output PinsCombinatorial Delays from Input Pins to Output Pins Maximum FrequencyInput Clock Jitter Tolerance Delay Path Variation4 Delay-Locked Loop DLLDigital Clock Manager DCM Timing Recommended Operating Conditions for the DLLSpeed Grade Symbol Description Speed Grade Symbol Description Units Min Max Switching Characteristics for the DFSDigital Frequency Synthesizer DFS Recommended Operating Conditions for the DFSSwitching Characteristics for the PS in Variable Phase Mode Phase Shifter PSPhase Shifting Range Miscellaneous DCM TimingDnaport Interface Timing DNA Port TimingEntering Suspend Mode Exiting Suspend Mode Suspend Mode TimingEntering Suspend Mode Symbol Description Min Typ Max UnitsGeneral Configuration Power-On/Reconfigure Timing Configuration and Jtag TimingAll Speed Grades Symbol Description Device Min Max Units Master Mode Cclk Output Period by ConfigRate Option Setting Configuration Clock Cclk CharacteristicsCclk clock period by 11.2Slave Mode Cclk Input Low and High Time Master Mode Cclk Output Minimum Low and High TimeEquivalent Cclk clock frequency Cclk Low and High timeSlave All Speed Grades Symbol Description Master Serial and Slave Serial Mode TimingMin Max Units Clock-to-Output Times Slave Parallel Mode Timing Symbol Description Minimum Serial Peripheral Interface SPI Configuration TimingSymbol Description Requirement Units Symbol Description Minimum Maximum Units Byte Peripheral Interface BPI Configuration TimingSetup time on M20 mode pins before the rising edge of Initb Hold time on M20 mode pins after the rising edge of InitbParallel NOR Flash Prom output-enable time Symbol Description Requirement UnitsParallel NOR Flash Prom read access time Parallel NOR Flash Prom chip-select timeINTEST, EXTEST, Sample Ieee 1149.1/1553 Jtag Test Access Port TimingDSP48A timing in and Table Diffhstli and Diffhstliii to , , and . Updated Tmds DCDC and Switching Characteristics Pin Types Types of Pins on Spartan-3A DSP FPGAsType/Color Description Pin Names in Type Code Pinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Package Pins by TypePower and Ground Supply Pins by Package Maximum User I/O by PackageSpartan-3A DSP Package Thermal Characteristics Package Thermal CharacteristicsPinout Descriptions Pinout Table CS484 484-Ball Chip-Scale Ball Grid ArraySpartan-3A DSP CS484 Pinout Bank Pin Name CS484 Type BallPinout Descriptions Spartan-3A DSP CS484 Pinout AA3 Dual VCCO1AA4 AA6 InputVCCO2 VCCO2 AA5 Vcco AA9VCCO2 Vcco AA1 VrefGND AA7 VCCO3 VccoGND AB1 Vccaux TCK Vccaux Progb Config DoneJtag Vccaux TMS Jtag TDOFootprint Migration Differences User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the CS484 Package User I/Os Per Bank for the XC3SD3400A in the CS484 PackageLeft Half of Package top view CS484 FootprintRight Half of CS484 Package top view Pinout Table FG676 676-Ball Fine-Pitch Ball Grid ArraySpartan-3A DSP FG676 Pinout for Spartan-3A DSP FG676 Pinout for XC3SD1800A FpgaIOL26N0/GCLK7 IOL26P0/GCLK6IOL30P1/RHCLK0 IOL30N1/RHCLK1IOL33P1/RHCLK4 IOL31P1/RHCLK2IOL27P2/GCLK0 IOL17P2/RDWRBAF4 AF3AF5 AF7 InputAB9 IP2/VREF2 AB6 VrefIOL30N2/MOSI/CSIB IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 VrefIOL34N3/LHCLK5 IOL33P3/LHCLK2IOL34P3/LHCLK4 IOL35N3/LHCLK7AE2 Vref AE1 InputAD1 AD2GND AF1 AF6 Vccaux Progb Config TDI Jtag TDOGND AD3 AD8 GND AA1 AA6User I/Os Per Bank for the XC3SD1800A in the FG676 Package User I/Os by BankTop 128 Right 519 314FG676 Package Footprint for XC3SD1800A Fpga top view FG676 FootprintTDO Bank XC3SD3400A Pin Name FG676 Type Ball Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaIOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 IOL01P0 G20IP1/VREF1 VCCO0 Vcco IOL01P1/HDCIOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16 IOL34P1/IRDY1/RHCLK6T25 IOL05N1 AC25 IOL06P1IOL12P2 Y10 IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 VCCO2 AF7 Vcco AE5IOL36N3 IOL37P3 IOL53P3 IOL53N3 IP3IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IOL10N3 IOL03N3 IP3 IP3/VREF3 VrefAA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND GND AC5 AC7 GND AD3 AD5 AD8GND AB3 GND AA1 AA4 AA6Vccint AA8 Vccaux AF2 AB4 AB5User I/Os Per Bank for the XC3SD3400A in the FG676 Package Vref are on Input pinsTop 111 Right Bottom 112 LeftPinout Descriptions FG676 Package Footprint for XC3SD3400A Fpga top viewVCCO0 VREF1 VREF1 FG676 Footprint Migration DifferencesPinout Descriptions FG676 Footprint Migration Differences Migration RecommendationsFpga and XC3SD3400A Fpga . Minor edits SPARTAN-3A DSPPinout Descriptions