Xilinx DS610 manual Slave Parallel Mode Timing

R

DC and Switching Characteristics

Slave Parallel Mode Timing

PROG_B
(Input)
INIT_B
(Open-Drain)
	TSMCSCC		T	SMCCCS
CSI_B
(Input)	TSMCCW
				TSMWCC
RDWR_B
(Input)		TMCCH
			TMCCL
		TSCCH	TSCCL
CCLK
(Input)			1/FCCPAR
	TSMDCC	TSMCCD
D0 - D7	Byte 0	Byte 1	Byte n Byte n+1

(Inputs)

DS529-3_02_051607

Notes:

1.It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B switches High, be careful to avoid contention on the D0 - D7 bus.

Figure 12: Waveforms for Slave Parallel Configuration

Table 50: Timing for the Slave Parallel Configuration Mode

			All Speed Grades
Symbol		Description	Min	Max	Units
Setup Times
TSMDCC(2)	The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin		7	-	ns
TSMCSCC	Setup time on the CSI_B pin before the rising transition at the CCLK pin		7	-	ns
TSMCCW	Setup time on the RDWR_B pin before the rising transition at the CCLK pin		17	-	ns
Hold Times
TSMCCD	The time from the rising transition at the CCLK pin to the point when data is last held at		1	-	ns
	the D0-D7 pins
TSMCCCS	The time from the rising transition at the CCLK pin to the point when a logic level is last		0	-	ns
	held at the CSO_B pin
TSMWCC	The time from the rising transition at the CCLK pin to the point when a logic level is last		0	-	ns
	held at the RDWR_B pin
Clock Timing
TCCH	The High pulse width at the CCLK input pin		5	-	ns
TCCL	The Low pulse width at the CCLK input pin		5	-	ns
FCCPAR	Frequency of the clock signal	No bitstream compression	0	80	MHz
	at the CCLK input pin
		With bitstream compression	0	80	MHz

Notes:

1.The numbers in this table are based on the operating conditions set forth in Table 7.

2.Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.

DS610-3 (v2.0) July 16, 2007 www.xilinx.com 51

Product Specification