Xilinx DS610 manual Clock to Out from Pipeline Register Clock to Output Pins, Maximum Frequency

DC and Switching Characteristics

Table 34: Clock to Out, Propagation Delays, and Maximum Frequency for the DSP48A

R

					Speed Grade
					-5	-4
Symbol	Description	Preadder	Multiplier	Postadder	Max	Max	Units
Clock to Out from Output Register Clock to Output Pin
TDSPCKO_PP	CLK (PREG) to P output	-	-	-	1.26	1.44	ns
Clock to Out from Pipeline Register Clock to Output Pins
TDSPCKO_PM	CLK (MREG) to P output	-	Yes	Yes	3.16	3.63	ns
		-	Yes	No	1.94	2.23	ns
Clock to Out from Input Register Clock to Output Pins
TDSPCKO_PA	CLK (AREG) to P output	-	Yes	Yes	6.33	7.27	ns
TDSPCKO_PB	CLK (BREG) to P output	Yes	Yes	Yes	7.45	8.56	ns
TDSPCKO_PC	CLK (CREG) to P output	-	-	Yes	3.37	3.87	ns
TDSPCKO_PD	CLK (DREG) to P output	Yes	Yes	Yes	7.33	8.42	ns
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_AP	A or B input to P output	-	No	Yes	2.78	3.19	ns
TDSPDO_BP		-	Yes	No	4.59	5.28	ns
		-	Yes	Yes	5.65	6.49	ns
TDSPDO_BP	B input to P output	Yes	No	No	3.49	4.01	ns
		Yes	Yes	No	5.79	6.65	ns
		Yes	Yes	Yes	6.74	7.74	ns
TDSPDO_CP	C input to P output	-	-	Yes	2.76	3.17	ns
TDSPDO_DP	D input to P output	Yes	Yes	Yes	6.81	7.82	ns
TDSPDO_OPP	OPMODE input to P output	Yes	Yes	Yes	7.12	8.18	ns
Maximum Frequency
FMAX	All registers used	Yes	Yes	Yes	287	250	MHz
	A1REG or B1REG to PREG	-	Yes	No	246	214	MHz
		-	Yes	Yes	195	170	MHz
	DREG, A0REG, or B0REG to MREG	Yes	Yes	-	205	178	MHz

40	www.xilinx.com	DS610-3 (v2.0) July 16, 2007
		Product Specification