Xilinx DS610 manual Test Logic Level Conditions Characteristics, Attribute Max Min

Page 16

DC and Switching Characteristics

R

Table 11: DC Characteristics of User I/Os Using

Single-Ended Standards

 

 

 

Test

Logic Level

 

 

 

 

Conditions

Characteristics

 

 

 

 

 

 

IOSTANDARD

IOL

IOH

VOL

 

VOH

Attribute

 

(mA)

(mA)

Max (V)

 

Min (V)

 

 

 

 

 

 

 

LVTTL(3)

 

2

2

–2

0.4

 

2.4

 

 

4

4

–4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

6

–6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

8

–8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

12

–12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

16

–16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

24

24

–24

 

 

 

 

 

 

 

 

 

 

 

LVCMOS33(3)

 

2

2

–2

0.4

VCCO – 0.4

 

 

4

4

–4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

6

–6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

8

–8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

12

–12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

16

–16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

24(4)

24

–24

 

 

 

 

LVCMOS25(3)

 

2

2

–2

0.4

VCCO – 0.4

 

 

4

4

–4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

6

–6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

8

–8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

12

–12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16(4)

16

–16

 

 

 

 

 

 

24(4)

24

–24

 

 

 

 

LVCMOS18(3)

 

2

2

–2

0.45

V

 

– 0.45

 

 

 

 

 

 

CCO

 

 

 

4

4

–4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

6

–6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

8

–8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12(4)

12

–12

 

 

 

 

 

 

16(4)

16

–16

 

 

 

 

LVCMOS15(3)

 

2

2

–2

0.25 • VCCO

0.75 • VCCO

 

 

4

4

–4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

6

–6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8(4)

8

–8

 

 

 

 

 

 

12(4)

12

–12

 

 

 

 

LVCMOS12(3)

 

2

2

–2

0.4

VCCO – 0.4

 

 

4(4)

4

–4

 

 

 

 

 

 

6(4)

6

–6

 

 

 

 

Table 11: DC Characteristics of User I/Os Using

Single-Ended Standards (Continued)

 

Test

Logic Level

 

 

 

Conditions

Characteristics

 

 

 

 

 

 

 

IOSTANDARD

IOL

IOH

VOL

 

VOH

Attribute

(mA)

(mA)

Max (V)

 

Min (V)

PCI33_3(5)

1.5

–0.5

10% V

90% V

CCO

 

 

 

CCO

 

 

 

 

PCI66_3(5)

1.5

–0.5

10% V

90% V

CCO

 

 

 

CCO

 

 

 

 

PCIX

1.5

–0.5

10% VCCO

90% VCCO

HSTL_I(4)

8

–8

0.4

V

CCO

- 0.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HSTL_III(4)

24

–8

0.4

V

CCO

- 0.4

 

 

 

 

 

 

 

 

 

 

 

 

HSTL_I_18

8

–8

0.4

VCCO - 0.4

HSTL_II_18(4)

16

–16

0.4

V

CCO

- 0.4

 

 

 

 

 

 

 

 

 

 

 

 

HSTL_III_18

24

–8

0.4

VCCO - 0.4

SSTL18_I

6.7

–6.7

VTT – 0.475

VTT + 0.475

 

 

 

 

 

SSTL18_II(4)

13.4

–13.4

VTT – 0.475

VTT + 0.475

SSTL2_I

8.1

–8.1

VTT – 0.61

VTT + 0.61

SSTL2_II(4)

16.2

–16.2

V – 0.80

V

TT

+ 0.80

 

 

 

TT

 

 

 

 

SSTL3_I

8

–8

VTT – 0.6

VTT + 0.6

SSTL3_II(4)

16

–16

VTT – 0.8

VTT + 0.8

Notes:

1.The numbers in this table are based on the conditions set forth in Table 7 and Table 10.

2.Descriptions of the symbols used in this table are as follows:

IOL – the output current condition under which VOL is tested IOH – the output current condition under which VOH is tested VOL – the output voltage that indicates a Low logic level VOH – the output voltage that indicates a High logic level VIL – the input voltage that indicates a Low logic level

VIH – the input voltage that indicates a High logic level VCCO – the supply voltage for output drivers

VREF – the reference voltage for setting the input switching threshold VTT – the voltage applied to a resistor termination

3.For the LVCMOS and LVTTL standards: the same VOL and VOH limits apply for both the Fast and Slow slew attributes.

4.These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.

5.Tested according to the relevant PCI specifications.

16

www.xilinx.com

DS610-3 (v2.0) July 16, 2007

 

 

Product Specification

Page 15 Page 17
Image 16
Page 15 Page 17
Contents Product Specification DS610-1 v2.0 July 16DS610-2 v2.0 July 16 DS610-3 v2.0 July 16Data Sheet Introduction FeaturesSpartan-3A and Spartan-3A DSP Fpga Differences Configuration Architectural OverviewCapabilities Introduction and Ordering InformationDCM CS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A519 227 XC3SD3400APackage Marking Ordering InformationStandard Packaging Pb-Free PackagingRevision History Date Version RevisionIntroduction and Ordering Information Added Low-power options no changes to this module DS610-2 v2.0 July 16Functional Description DC Electrical Characteristics Symbol Description Conditions Min Max UnitsAbsolute Maximum Ratings Absolute Maximum RatingsPower Supply Specifications DC and Switching CharacteristicsSupply Voltage Thresholds for Power-On Reset Symbol Description Min Max UnitsSymbol Description Test Conditions Min Typ Max Units General DC Characteristics for I/O Pins= GND Quiescent Supply Current Characteristics Typical2 Commercial Industrial Symbol Description DeviceQuiescent Current Requirements Maximum2CCO for Drivers Single-Ended I/O StandardsAttribute Min Nom Max Test Logic Level Conditions Characteristics AttributeTest Logic Level Conditions Attribute Max MinIostandard Attribute CCO for Drivers Differential I/O StandardsMin Nom Max Min mV Nom mV Max mV Iostandard Attribute Min mV Typ mV Max mV Device DNA Identifier Memory Characteristics Symbol Description Minimum UnitsDevice DNA Data Retention, Read Endurance External Termination Requirements for Differential I/OSwitching Characteristics Software Version RequirementsSpartan-3A DSP Speed File Version History Sign Up for Alerts on Xilinx MySupportSpartan-3A DSP v1.29 Speed Grade Designations Timing Pin-to-Pin Clock-to-Output Times for the IOB Output PathRate, without DCM At the Output pin. The DCM is not UseIfddelayvalue = Hold TimesSymbol Description Conditions Device Min Units Setup TimesSet/Reset Pulse Width Speed GradeIoplid Single-Ended Standards Lvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12PCI333 PCI663 Differential StandardsAsynchronous Output Enable/Disable Times Set/Reset TimesTiming for the IOB Three-State Path QuietIO 27.67 QuietIOQuietIO 25.92 QuietIO 24.97LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25 Inputs OnlySignal Standard Inputs Outputs Timing Measurement MethodologyTest Methods for Timing Measurement at I/Os InputsDifferential RT ΩVicm + Equivalent VCCO/GND Pairs per Bank Simultaneously Switching Output GuidelinesDevice CS484 FG676 XC3SD1800A XC3SD3400A Package Type Signal Standard Top, Bottom Left, RightCS484, FG676 QuietIO PCI333 PCI663 Differential Standards Number of I/O Pairs or ChannelsCLB Slicem Timing Configurable Logic Block CLB TimingClock Timing CLB Shift Register Switching Characteristics Clock Buffer/Multiplexer Switching CharacteristicsClock Distribution Switching Characteristics Block RAM Timing Block RAM TimingClock Frequency Setup Times for the DSP48A Speed Grade Symbol DescriptionSetup Times of Data Pins to the Pipeline Register Clock DSP48A TimingClock to Out from Pipeline Register Clock to Output Pins Clock to Out from Input Register Clock to Output PinsCombinatorial Delays from Input Pins to Output Pins Maximum FrequencyDelay-Locked Loop DLL Input Clock Jitter Tolerance Delay Path Variation4Digital Clock Manager DCM Timing Recommended Operating Conditions for the DLLSpeed Grade Symbol Description Switching Characteristics for the DFS Speed Grade Symbol Description Units Min MaxDigital Frequency Synthesizer DFS Recommended Operating Conditions for the DFSPhase Shifter PS Switching Characteristics for the PS in Variable Phase ModePhase Shifting Range Miscellaneous DCM TimingDNA Port Timing Dnaport Interface TimingSuspend Mode Timing Entering Suspend Mode Exiting Suspend ModeEntering Suspend Mode Symbol Description Min Typ Max UnitsGeneral Configuration Power-On/Reconfigure Timing Configuration and Jtag TimingAll Speed Grades Symbol Description Device Min Max Units Configuration Clock Cclk Characteristics Master Mode Cclk Output Period by ConfigRate Option SettingCclk clock period by 11.2Master Mode Cclk Output Minimum Low and High Time Slave Mode Cclk Input Low and High TimeEquivalent Cclk clock frequency Cclk Low and High timeSlave All Speed Grades Symbol Description Master Serial and Slave Serial Mode TimingMin Max Units Clock-to-Output Times Slave Parallel Mode Timing Serial Peripheral Interface SPI Configuration Timing Symbol Description MinimumSymbol Description Requirement Units Byte Peripheral Interface BPI Configuration Timing Symbol Description Minimum Maximum UnitsSetup time on M20 mode pins before the rising edge of Initb Hold time on M20 mode pins after the rising edge of InitbSymbol Description Requirement Units Parallel NOR Flash Prom output-enable timeParallel NOR Flash Prom read access time Parallel NOR Flash Prom chip-select timeIeee 1149.1/1553 Jtag Test Access Port Timing INTEST, EXTEST, SampleDiffhstli and Diffhstliii to , , and . Updated Tmds DC DSP48A timing in and TableDC and Switching Characteristics Pin Types Types of Pins on Spartan-3A DSP FPGAsType/Color Description Pin Names in Type Code Package Pins by Type Pinout Descriptions Types of Pins on Spartan-3A DSP FPGAsPower and Ground Supply Pins by Package Maximum User I/O by PackageSpartan-3A DSP Package Thermal Characteristics Package Thermal CharacteristicsPinout Descriptions CS484 484-Ball Chip-Scale Ball Grid Array Pinout TableSpartan-3A DSP CS484 Pinout Bank Pin Name CS484 Type BallPinout Descriptions Spartan-3A DSP CS484 Pinout VCCO1 AA3 DualAA4 AA6 InputVCCO2 AA5 Vcco AA9 VCCO2VCCO2 Vcco AA1 VrefGND AA7 VCCO3 VccoGND AB1 Vccaux Progb Config Done Vccaux TCKJtag Vccaux TMS Jtag TDOUser I/Os by Bank Footprint Migration DifferencesUser I/Os Per Bank for the XC3SD1800A in the CS484 Package User I/Os Per Bank for the XC3SD3400A in the CS484 PackageCS484 Footprint Left Half of Package top viewRight Half of CS484 Package top view FG676 676-Ball Fine-Pitch Ball Grid Array Pinout TableSpartan-3A DSP FG676 Pinout for Spartan-3A DSP FG676 Pinout for XC3SD1800A FpgaIOL26P0/GCLK6 IOL26N0/GCLK7IOL30N1/RHCLK1 IOL30P1/RHCLK0IOL33P1/RHCLK4 IOL31P1/RHCLK2IOL17P2/RDWRB IOL27P2/GCLK0AF3 AF4AF5 AF7 InputIP2/VREF2 AB6 Vref AB9IOL30N2/MOSI/CSIB IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 VrefIOL33P3/LHCLK2 IOL34N3/LHCLK5IOL34P3/LHCLK4 IOL35N3/LHCLK7AE1 Input AE2 VrefAD1 AD2Vccaux Progb Config TDI Jtag TDO GND AF1 AF6GND AD3 AD8 GND AA1 AA6User I/Os by Bank User I/Os Per Bank for the XC3SD1800A in the FG676 PackageTop 128 Right 519 314FG676 Footprint FG676 Package Footprint for XC3SD1800A Fpga top viewTDO Spartan-3A DSP FG676 Pinout for XC3SD3400A Fpga Bank XC3SD3400A Pin Name FG676 Type BallIOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 IOL01P0 G20VCCO0 Vcco IOL01P1/HDC IP1/VREF1IOL34P1/IRDY1/RHCLK6 IOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16T25 IOL05N1 AC25 IOL06P1IOL12P2 Y10 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13 IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 VCCO2 AF7 Vcco AE5IOL36N3 IOL37P3 IOL53P3 IOL53N3 IP3IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IOL10N3 IOL03N3 IP3 IP3/VREF3 VrefAA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND GND AD3 AD5 AD8 GND AC5 AC7GND AB3 GND AA1 AA4 AA6Vccaux AF2 AB4 AB5 Vccint AA8Vref are on Input pins User I/Os Per Bank for the XC3SD3400A in the FG676 PackageTop 111 Right Bottom 112 LeftFG676 Package Footprint for XC3SD3400A Fpga top view Pinout DescriptionsVCCO0 VREF1 FG676 Footprint Migration Differences VREF1Migration Recommendations Pinout Descriptions FG676 Footprint Migration DifferencesSPARTAN-3A DSP Fpga and XC3SD3400A Fpga . Minor editsPinout Descriptions
Top Page Image Contents