Xilinx DS610 manual Symbol Description Requirement Units, Parallel NOR Flash Prom chip-select time

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DC and Switching Characteristics

Table 54: Configuration Timing Requirements for Attached Parallel NOR Flash

Symbol	Description		Requirement			Units
TCE	Parallel NOR Flash PROM chip-select time		TCE ≤	TIN ITADDR		ns
(tELQV)
TOE	Parallel NOR Flash PROM output-enable time		TOE ≤	TINITAD DR		ns
(tGLQV)
TACC	Parallel NOR Flash PROM read access time	TACC	≤ TCCL Kn(min) – TCC O –		TDCC – PCB	ns
(tAVQV)
TBYTE	For x8/x16 PROMs only: BYTE# to output valid time(3)		TBYTE ≤	TINITAD DR		ns
(tFLQV, tFHQV)

Notes:

1.These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.

2.Subtract additional printed circuit board routing delay as required by the application.

3.The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor value also depends on whether the FPGA’s PUDC_B pin is High or Low.

DS610-3 (v2.0) July 16, 2007 www.xilinx.com 55

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