Xilinx DS610 manual Block RAM Timing, Clock Frequency

Page 38

DC and Switching Characteristics

R

Block RAM Timing

Table 32: Block RAM Timing

				Speed Grade

		-5				-4

Symbol	Description	Min		Max	Min		Max	Units
Clock-to-Output Times

TRCKO_DOA_NC	When reading from block RAM, the delay from the active	-		2.38	-		2.80	ns
	transition at the CLK input to data appearing at the DOUT
	output
TRCKO_DOA	Clock CLK to DOUT output (with output register)	-		1.24	-		1.45	ns
Setup Times

TRCCK_ADDR	Setup time for the ADDR inputs before the active transition	0.40		-	0.46		-	ns
	at the CLK input of the block RAM
TRDCK_DIB	Setup time for data at the DIN inputs before the active	0.29		-	0.33		-	ns
	transition at the CLK input of the block RAM
TRCCK_ENB	Setup time for the EN input before the active transition at the	0.51		-	0.60		-	ns
	CLK input of the block RAM
TRCCK_WEB	Setup time for the WE input before the active transition at the	0.64		-	0.75		-	ns
	CLK input of the block RAM
TRCCK_REGCE	Setup time for the CE input before the active transition at the	0.34		-	0.40		-	ns
	CLK input of the block RAM
TRCCK_RST	Setup time for the RST input before the active transition at	0.22		-	0.25		-	ns
	the CLK input of the block
Hold Times

TRCKC_ADDR	Hold time on the ADDR inputs after the active transition at	0.09		-	0.10		-	ns
	the CLK input
TRDCK_DIB	Hold time on the DIN inputs after the active transition at the	0.09		-	0.10		-	ns
	CLK input
TRCKC_ENB	Hold time on the EN input after the active transition at the	0.09		-	0.10		-	ns
	CLK input
TRCKC_WEB	Hold time on the WE input after the active transition at the	0.09		-	0.10		-	ns
	CLK input
TRCKC_REGCE	Hold time on the CE input after the active transition at the	0.09		-	0.10		-	ns
	CLK input
TRCKC_RST	Hold time on the RST input after the active transition at the	0.09		-	0.10		-	ns
	CLK input
Clock Timing

TBPWH	High pulse width of the CLK signal	1.56		-	1.79		-	ns
TBPWL	Low pulse width of the CLK signal	1.56		-	1.79		-	ns
Clock Frequency

FBRAM	Block RAM clock frequency.	0		320	0		280	MHz

Notes:

1.The numbers in this table are based on the operating conditions set forth in Table 7.

38	www.xilinx.com	DS610-3 (v2.0) July 16, 2007
		Product Specification

Image 38

Contents DS610-2 v2.0 July 16 Product SpecificationDS610-1 v2.0 July 16 DS610-3 v2.0 July 16Data Sheet Spartan-3A and Spartan-3A DSP Fpga Differences FeaturesIntroduction Capabilities ConfigurationArchitectural Overview Introduction and Ordering Information519 227 DCMCS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A XC3SD3400AStandard Packaging Package MarkingOrdering Information Pb-Free PackagingRevision History Date Version RevisionIntroduction and Ordering Information Added Low-power options no changes to this module DS610-2 v2.0 July 16Functional Description Absolute Maximum Ratings DC Electrical CharacteristicsSymbol Description Conditions Min Max Units Absolute Maximum RatingsSupply Voltage Thresholds for Power-On Reset Power Supply SpecificationsDC and Switching Characteristics Symbol Description Min Max Units= GND General DC Characteristics for I/O PinsSymbol Description Test Conditions Min Typ Max Units Quiescent Current Requirements Quiescent Supply Current CharacteristicsTypical2 Commercial Industrial Symbol Description Device Maximum2Attribute Min Nom Max Single-Ended I/O StandardsCCO for Drivers Test Logic Level Conditions Test Logic Level Conditions CharacteristicsAttribute Attribute Max MinMin Nom Max Min mV Nom mV Max mV Differential I/O StandardsIostandard Attribute CCO for Drivers Iostandard Attribute Min mV Typ mV Max mV Device DNA Data Retention, Read Endurance Device DNA Identifier Memory CharacteristicsSymbol Description Minimum Units External Termination Requirements for Differential I/OSwitching Characteristics Software Version RequirementsSpartan-3A DSP v1.29 Speed Grade Designations Sign Up for Alerts on Xilinx MySupportSpartan-3A DSP Speed File Version History Rate, without DCM TimingPin-to-Pin Clock-to-Output Times for the IOB Output Path At the Output pin. The DCM is not UseIfddelayvalue = Hold TimesSet/Reset Pulse Width Symbol Description ConditionsDevice Min Units Setup Times Speed GradeIoplid PCI333 PCI663 Single-Ended StandardsLvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 Differential StandardsTiming for the IOB Three-State Path Set/Reset TimesAsynchronous Output Enable/Disable Times QuietIO 27.67 QuietIOQuietIO 25.92 QuietIO 24.97LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25 Inputs OnlyTest Methods for Timing Measurement at I/Os Signal Standard Inputs OutputsTiming Measurement Methodology InputsVicm + RT ΩDifferential Device CS484 FG676 XC3SD1800A XC3SD3400A Simultaneously Switching Output GuidelinesEquivalent VCCO/GND Pairs per Bank CS484, FG676 Signal Standard Top, Bottom Left, RightPackage Type QuietIO PCI333 PCI663 Differential Standards Number of I/O Pairs or ChannelsClock Timing Configurable Logic Block CLB TimingCLB Slicem Timing Clock Distribution Switching Characteristics Clock Buffer/Multiplexer Switching CharacteristicsCLB Shift Register Switching Characteristics Clock Frequency Block RAM TimingBlock RAM Timing Setup Times of Data Pins to the Pipeline Register Clock Setup Times for the DSP48ASpeed Grade Symbol Description DSP48A TimingCombinatorial Delays from Input Pins to Output Pins Clock to Out from Pipeline Register Clock to Output PinsClock to Out from Input Register Clock to Output Pins Maximum FrequencyDigital Clock Manager DCM Timing Delay-Locked Loop DLLInput Clock Jitter Tolerance Delay Path Variation4 Recommended Operating Conditions for the DLLSpeed Grade Symbol Description Digital Frequency Synthesizer DFS Switching Characteristics for the DFSSpeed Grade Symbol Description Units Min Max Recommended Operating Conditions for the DFSPhase Shifting Range Phase Shifter PSSwitching Characteristics for the PS in Variable Phase Mode Miscellaneous DCM TimingDNA Port Timing Dnaport Interface TimingEntering Suspend Mode Suspend Mode TimingEntering Suspend Mode Exiting Suspend Mode Symbol Description Min Typ Max UnitsAll Speed Grades Symbol Description Device Min Max Units Configuration and Jtag TimingGeneral Configuration Power-On/Reconfigure Timing Cclk clock period by Configuration Clock Cclk CharacteristicsMaster Mode Cclk Output Period by ConfigRate Option Setting 11.2Equivalent Cclk clock frequency Master Mode Cclk Output Minimum Low and High TimeSlave Mode Cclk Input Low and High Time Cclk Low and High timeMin Max Units Clock-to-Output Times Master Serial and Slave Serial Mode TimingSlave All Speed Grades Symbol Description Slave Parallel Mode Timing Serial Peripheral Interface SPI Configuration Timing Symbol Description MinimumSymbol Description Requirement Units Setup time on M20 mode pins before the rising edge of Initb Byte Peripheral Interface BPI Configuration TimingSymbol Description Minimum Maximum Units Hold time on M20 mode pins after the rising edge of InitbParallel NOR Flash Prom read access time Symbol Description Requirement UnitsParallel NOR Flash Prom output-enable time Parallel NOR Flash Prom chip-select timeIeee 1149.1/1553 Jtag Test Access Port Timing INTEST, EXTEST, SampleDiffhstli and Diffhstliii to , , and . Updated Tmds DC DSP48A timing in and TableDC and Switching Characteristics Type/Color Description Pin Names in Type Code Types of Pins on Spartan-3A DSP FPGAsPin Types Power and Ground Supply Pins by Package Package Pins by TypePinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Maximum User I/O by PackagePinout Descriptions Package Thermal CharacteristicsSpartan-3A DSP Package Thermal Characteristics Spartan-3A DSP CS484 Pinout CS484 484-Ball Chip-Scale Ball Grid ArrayPinout Table Bank Pin Name CS484 Type BallPinout Descriptions Spartan-3A DSP CS484 Pinout AA4 VCCO1AA3 Dual AA6 InputVCCO2 Vcco VCCO2 AA5 Vcco AA9VCCO2 AA1 VrefGND AB1 VCCO3 VccoGND AA7 Jtag Vccaux Progb Config DoneVccaux TCK Vccaux TMS Jtag TDOUser I/Os Per Bank for the XC3SD1800A in the CS484 Package User I/Os by BankFootprint Migration Differences User I/Os Per Bank for the XC3SD3400A in the CS484 PackageCS484 Footprint Left Half of Package top viewRight Half of CS484 Package top view Spartan-3A DSP FG676 Pinout for FG676 676-Ball Fine-Pitch Ball Grid ArrayPinout Table Spartan-3A DSP FG676 Pinout for XC3SD1800A FpgaIOL26P0/GCLK6 IOL26N0/GCLK7IOL33P1/RHCLK4 IOL30N1/RHCLK1IOL30P1/RHCLK0 IOL31P1/RHCLK2IOL17P2/RDWRB IOL27P2/GCLK0AF5 AF3AF4 AF7 InputIOL30N2/MOSI/CSIB IP2/VREF2 AB6 VrefAB9 IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 VrefIOL34P3/LHCLK4 IOL33P3/LHCLK2IOL34N3/LHCLK5 IOL35N3/LHCLK7AD1 AE1 InputAE2 Vref AD2GND AD3 AD8 Vccaux Progb Config TDI Jtag TDOGND AF1 AF6 GND AA1 AA6Top 128 Right User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the FG676 Package 519 314FG676 Footprint FG676 Package Footprint for XC3SD1800A Fpga top viewTDO IOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaBank XC3SD3400A Pin Name FG676 Type Ball IOL01P0 G20VCCO0 Vcco IOL01P1/HDC IP1/VREF1IOL34P1/IRDY1/RHCLK6 IOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16IOL12P2 Y10 IOL05N1 AC25 IOL06P1T25 IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 VCCO2 AF7 Vcco AE5IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IOL53P3 IOL53N3 IP3IOL36N3 IOL37P3 AA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND IP3/VREF3 VrefIOL10N3 IOL03N3 IP3 GND AB3 GND AD3 AD5 AD8GND AC5 AC7 GND AA1 AA4 AA6Vccaux AF2 AB4 AB5 Vccint AA8Top 111 Right Vref are on Input pinsUser I/Os Per Bank for the XC3SD3400A in the FG676 Package Bottom 112 LeftFG676 Package Footprint for XC3SD3400A Fpga top view Pinout DescriptionsVCCO0 VREF1 FG676 Footprint Migration Differences VREF1Migration Recommendations Pinout Descriptions FG676 Footprint Migration DifferencesSPARTAN-3A DSP Fpga and XC3SD3400A Fpga . Minor editsPinout Descriptions