Xilinx DS610 manual Pin Types, Types of Pins on Spartan-3A DSP FPGAs

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Spartan-3A DSP FPGA Family: Pinout Descriptions

DS610-4 (v2.0) July 16, 2007

Product Specification

 

 

Introduction

This section describes how the various pins on a Spartan™-3A DSP FPGA connect within the supported component packages and provides device-specific thermal characteristics. For general information on the pin functions and the package characteristics, see the Packaging section in:

•UG331: Spartan-3 Generation FPGA User Guide http://www.xilinx.com/bvdocs/userguides/ug331.pdf

Spartan-3A DSP FPGAs are available in both standard and Pb-free, RoHS versions of each package, with the Pb-free version adding a “G” to the middle of the package code.

Table 56: Types of Pins on Spartan-3A DSP FPGAs

Except for the thermal characteristics, all information for the standard package applies equally to the Pb-free package.

Pin Types

Most pins on a Spartan-3A DSP FPGA are general-purpose, user-defined I/O pins. There are, however, up to 12 different functional types of pins on Spartan-3A DSP packages, as outlined in Table 56. In the package footprint drawings that follow, the individual pins are color-coded according to pin type as in the table.

Type/Color

Description

Pin Name(s) in Type

Code

 

 

I/O

Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form

IO_#

differential I/Os.

IO_Lxxy_#

 

 

 

 

INPUT

Unrestricted, general-purpose input-only pin. This pin does not have an output structure

IP_#

or PCI clamp diode.

IP_Lxxy_#

 

 

Dual-purpose pin used in some configuration modes during the configuration process and

M[2:0]

 

then usually available as a user I/O after configuration. If the pin is not used during

PUDC_B

 

configuration, this pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation

CCLK

 

Configuration User Guide for additional information on these signals.

MOSI/CSI_B

 

 

D[7:1]

 

 

D0/DIN

DUAL

 

CSO_B

 

 

RDWR_B

 

 

INIT_B

 

 

A[25:0]

 

 

VS[2:0]

 

 

LDC[2:0]

 

 

HDC

 

Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other

IP/VREF_#

VREF

VREF pins in the same bank, provides a reference voltage input for certain I/O standards.

IP_Lxxy_#/VREF_#

If used for a reference voltage within a bank, all VREF pins within the bank must be

IO/VREF_#

 

 

connected.

IO_Lxxy_#/VREF_#

 

 

 

 

Either a user-I/O pin or an input to a specific clock buffer driver. Packages have 16 global

IO_Lxxy_#/GCLK[15:0],

CLK

clock inputs that optionally clock the entire device. The RHCLK inputs optionally clock the

IO_Lxxy_#/LHCLK[7:0],

right half of the device. The LHCLK inputs optionally clock the left half of the device. See

IO_Lxxy_#/RHCLK[7:0]

 

the Using Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User

 

 

Guide for additional information on these signals.

 

 

Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every

DONE, PROG_B

CONFIG

package has two dedicated configuration pins. These pins are powered by VCCAUX. See

 

the UG332: Spartan-3 Generation Configuration User Guide for additional information on

 

 

 

 

the DONE and PROG_B signals.

 

 

 

 

PWR

Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated

SUSPEND, AWAKE

pin. AWAKE is a Dual-Purpose pin. Unless Suspend mode is enabled in the application,

 

MGMT

 

AWAKE is available as a user-I/O pin.

 

 

 

 

 

 

JTAG

Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has

TDI, TMS, TCK, TDO

four dedicated JTAG pins. These pins are powered by VCCAUX.

 

 

 

 

 

 

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Product Specification

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Contents DS610-3 v2.0 July 16 Product SpecificationDS610-1 v2.0 July 16 DS610-2 v2.0 July 16Data Sheet Spartan-3A and Spartan-3A DSP Fpga Differences FeaturesIntroduction Introduction and Ordering Information ConfigurationArchitectural Overview CapabilitiesXC3SD3400A DCMCS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A 519 227Pb-Free Packaging Package MarkingOrdering Information Standard PackagingDate Version Revision Revision HistoryIntroduction and Ordering Information DS610-2 v2.0 July 16 Added Low-power options no changes to this moduleFunctional Description Absolute Maximum Ratings DC Electrical CharacteristicsSymbol Description Conditions Min Max Units Absolute Maximum RatingsSymbol Description Min Max Units Power Supply SpecificationsDC and Switching Characteristics Supply Voltage Thresholds for Power-On Reset= GND General DC Characteristics for I/O PinsSymbol Description Test Conditions Min Typ Max Units Maximum2 Quiescent Supply Current CharacteristicsTypical2 Commercial Industrial Symbol Description Device Quiescent Current RequirementsAttribute Min Nom Max Single-Ended I/O StandardsCCO for Drivers Attribute Max Min Test Logic Level Conditions CharacteristicsAttribute Test Logic Level ConditionsMin Nom Max Min mV Nom mV Max mV Differential I/O StandardsIostandard Attribute CCO for Drivers Iostandard Attribute Min mV Typ mV Max mV External Termination Requirements for Differential I/O Device DNA Identifier Memory CharacteristicsSymbol Description Minimum Units Device DNA Data Retention, Read EnduranceSoftware Version Requirements Switching CharacteristicsSpartan-3A DSP v1.29 Speed Grade Designations Sign Up for Alerts on Xilinx MySupportSpartan-3A DSP Speed File Version History At the Output pin. The DCM is not Use TimingPin-to-Pin Clock-to-Output Times for the IOB Output Path Rate, without DCMHold Times Ifddelayvalue =Speed Grade Symbol Description ConditionsDevice Min Units Setup Times Set/Reset Pulse WidthIoplid Differential Standards Single-Ended StandardsLvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI333 PCI663Timing for the IOB Three-State Path Set/Reset TimesAsynchronous Output Enable/Disable Times QuietIO QuietIO 27.67QuietIO 24.97 QuietIO 25.92Inputs Only LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25Inputs Signal Standard Inputs OutputsTiming Measurement Methodology Test Methods for Timing Measurement at I/OsVicm + RT ΩDifferential Device CS484 FG676 XC3SD1800A XC3SD3400A Simultaneously Switching Output GuidelinesEquivalent VCCO/GND Pairs per Bank CS484, FG676 Signal Standard Top, Bottom Left, RightPackage Type Differential Standards Number of I/O Pairs or Channels QuietIO PCI333 PCI663Clock Timing Configurable Logic Block CLB TimingCLB Slicem Timing Clock Distribution Switching Characteristics Clock Buffer/Multiplexer Switching CharacteristicsCLB Shift Register Switching Characteristics Clock Frequency Block RAM TimingBlock RAM Timing DSP48A Timing Setup Times for the DSP48ASpeed Grade Symbol Description Setup Times of Data Pins to the Pipeline Register ClockMaximum Frequency Clock to Out from Pipeline Register Clock to Output PinsClock to Out from Input Register Clock to Output Pins Combinatorial Delays from Input Pins to Output PinsRecommended Operating Conditions for the DLL Delay-Locked Loop DLLInput Clock Jitter Tolerance Delay Path Variation4 Digital Clock Manager DCM TimingSpeed Grade Symbol Description Recommended Operating Conditions for the DFS Switching Characteristics for the DFSSpeed Grade Symbol Description Units Min Max Digital Frequency Synthesizer DFSMiscellaneous DCM Timing Phase Shifter PSSwitching Characteristics for the PS in Variable Phase Mode Phase Shifting RangeDnaport Interface Timing DNA Port TimingSymbol Description Min Typ Max Units Suspend Mode TimingEntering Suspend Mode Exiting Suspend Mode Entering Suspend ModeAll Speed Grades Symbol Description Device Min Max Units Configuration and Jtag TimingGeneral Configuration Power-On/Reconfigure Timing 11.2 Configuration Clock Cclk CharacteristicsMaster Mode Cclk Output Period by ConfigRate Option Setting Cclk clock period byCclk Low and High time Master Mode Cclk Output Minimum Low and High TimeSlave Mode Cclk Input Low and High Time Equivalent Cclk clock frequencyMin Max Units Clock-to-Output Times Master Serial and Slave Serial Mode TimingSlave All Speed Grades Symbol Description Slave Parallel Mode Timing Symbol Description Minimum Serial Peripheral Interface SPI Configuration TimingSymbol Description Requirement Units Hold time on M20 mode pins after the rising edge of Initb Byte Peripheral Interface BPI Configuration TimingSymbol Description Minimum Maximum Units Setup time on M20 mode pins before the rising edge of InitbParallel NOR Flash Prom chip-select time Symbol Description Requirement UnitsParallel NOR Flash Prom output-enable time Parallel NOR Flash Prom read access time INTEST, EXTEST, Sample Ieee 1149.1/1553 Jtag Test Access Port TimingDSP48A timing in and Table Diffhstli and Diffhstliii to , , and . Updated Tmds DCDC and Switching Characteristics Type/Color Description Pin Names in Type Code Types of Pins on Spartan-3A DSP FPGAsPin Types Maximum User I/O by Package Package Pins by TypePinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Power and Ground Supply Pins by PackagePinout Descriptions Package Thermal CharacteristicsSpartan-3A DSP Package Thermal Characteristics Bank Pin Name CS484 Type Ball CS484 484-Ball Chip-Scale Ball Grid ArrayPinout Table Spartan-3A DSP CS484 PinoutPinout Descriptions Spartan-3A DSP CS484 Pinout AA6 Input VCCO1AA3 Dual AA4AA1 Vref VCCO2 AA5 Vcco AA9VCCO2 VCCO2 VccoGND AB1 VCCO3 VccoGND AA7 Vccaux TMS Jtag TDO Vccaux Progb Config DoneVccaux TCK JtagUser I/Os Per Bank for the XC3SD3400A in the CS484 Package User I/Os by BankFootprint Migration Differences User I/Os Per Bank for the XC3SD1800A in the CS484 PackageLeft Half of Package top view CS484 FootprintRight Half of CS484 Package top view Spartan-3A DSP FG676 Pinout for XC3SD1800A Fpga FG676 676-Ball Fine-Pitch Ball Grid ArrayPinout Table Spartan-3A DSP FG676 Pinout forIOL26N0/GCLK7 IOL26P0/GCLK6IOL31P1/RHCLK2 IOL30N1/RHCLK1IOL30P1/RHCLK0 IOL33P1/RHCLK4IOL27P2/GCLK0 IOL17P2/RDWRBAF7 Input AF3AF4 AF5IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 Vref IP2/VREF2 AB6 VrefAB9 IOL30N2/MOSI/CSIBIOL35N3/LHCLK7 IOL33P3/LHCLK2IOL34N3/LHCLK5 IOL34P3/LHCLK4AD2 AE1 InputAE2 Vref AD1GND AA1 AA6 Vccaux Progb Config TDI Jtag TDOGND AF1 AF6 GND AD3 AD8519 314 User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the FG676 Package Top 128 RightFG676 Package Footprint for XC3SD1800A Fpga top view FG676 FootprintTDO IOL01P0 G20 Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaBank XC3SD3400A Pin Name FG676 Type Ball IOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0IP1/VREF1 VCCO0 Vcco IOL01P1/HDCIOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16 IOL34P1/IRDY1/RHCLK6IOL12P2 Y10 IOL05N1 AC25 IOL06P1T25 VCCO2 AF7 Vcco AE5 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IOL53P3 IOL53N3 IP3IOL36N3 IOL37P3 AA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND IP3/VREF3 VrefIOL10N3 IOL03N3 IP3 GND AA1 AA4 AA6 GND AD3 AD5 AD8GND AC5 AC7 GND AB3Vccint AA8 Vccaux AF2 AB4 AB5Bottom 112 Left Vref are on Input pinsUser I/Os Per Bank for the XC3SD3400A in the FG676 Package Top 111 RightPinout Descriptions FG676 Package Footprint for XC3SD3400A Fpga top viewVCCO0 VREF1 VREF1 FG676 Footprint Migration DifferencesPinout Descriptions FG676 Footprint Migration Differences Migration RecommendationsFpga and XC3SD3400A Fpga . Minor edits SPARTAN-3A DSPPinout Descriptions
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