Xilinx DS610 manual FG676 Footprint, FG676 Package Footprint for XC3SD1800A Fpga top view

Page 81

R

FG676 Footprint -

XC3SD1800A FPGA

Left Half of Package (top view)

I/O: Unrestricted,

314general-purpose user I/O.

INPUT: Unrestricted,

82general-purpose input pin.

DUAL: Configuration,

52AWAKE pins, then possible user I/O.

VREF: User I/O or input

39voltage reference for bank.

CLK: User I/O, input, or

32clock buffer input.

CONFIG: Dedicated

3configuration pins, SUSPEND pin.

JTAG: Dedicated JTAG

4port pins.

GND: Ground

77

VCCO: Output voltage

36supply for bank.

VCCINT: Internal core

23supply voltage (+1.2V).

VCCAUX: Auxiliary supply

14voltage.

Note: The boxes with triangles inside indicate pin differences from the XC3SD3400A device.

Please see the "Footprint Migration Differences" section for more information.

Pinout Descriptions

 

 

 

 

 

 

 

 

 

 

Bank 0

 

 

 

 

 

 

 

 

1

2

3

4

5

6

7

8

9

10

11

12

13

 

 

A

GND

PROG_

I/O

I/O

INPUT

GND

INPUT

I/O

I/O

I/O

GND

I/O

INPUT

 

 

∇

∇

 

 

B

L51P_0

L45P_0

L38P_0

L36P_0

L33P_0

L29P_0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B

I/O

I/O

I/O

I/O

VCCO_0

I/O

I/O

I/O

I/O

I/O

VCCO_0

I/O

I/O

 

 

L28P_0

 

 

L02N_3

L02P_3

L51N_0

L45N_0

L41P_0

L42P_0

L38N_0

L36N_0

L33N_0

L29N_0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GCLK10

 

 

 

INPUT

INPUT

 

INPUT

I/O

I/O

I/O

I/O

 

I/O

I/O

I/O

I/O

 

 

C

L04N_3

L04P_3

GND

GND

 

 

VREF_3

∇

L28N_0

 

 

∇

L44P_0

L41N_0

L42N_0

L40P_0

L34P_0

L32P_0

L30N_0

 

 

 

∇

 

 

 

 

 

 

 

 

 

 

GCLK11

 

 

 

INPUT

INPUT

I/O

 

INPUT

I/O

INPUT

I/O

I/O

I/O

I/O

 

I/O

 

 

D

L08N_3

L08P_3

TMS

INPUT

 

 

∇

L32N_0

 

 

 

∇

∇

L06P_3

 

L44N_0

VREF_0

L40N_0

L37N_0

L34N_0

VREF_0

 

L30P_0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

I/O

VCCO_3

I/O

I/O

VCCAUX

INPUT

I/O

VCCO_0

INPUT

I/O

INPUT

I/O

VCCO_0

 

 

∇

∇

 

 

L11P_3

L07P_3

L06N_3

L48N_0

L37P_0

L31P_0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

F

GND

I/O

I/O

I/O

I/O

GND

I/O

I/O

INPUT

INPUT

GND

I/O

I/O

 

 

L52P_0

∇

∇

L27P_0

 

 

L11N_3

L14N_3

L07N_3

L09P_3

L48P_0

L31N_0

 

 

 

 

 

VREF_0

 

GCLK8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INPUT

INPUT

I/O

I/O

INPUT

I/O

 

I/O

I/O

I/O

INPUT

I/O

I/O

 

 

G

L16N_3

L16P_3

L12P_3

TDI

 

 

L52N_0

L27N_0

 

 

 

∇

∇

L14P_3

L09N_3

∇

L03P_3

 

PUDC_B

L47P_0

L46P_0

VREF_0

L35P_0

GCLK9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

I/O

 

INPUT

 

I/O

I/O

 

I/O

I/O

 

I/O

 

 

 

H

GND

L12N_3

VCCO_3

GND

VCCO_0

INPUT

 

 

L17N_3

L17P_3

VREF_3

L10N_3

L03N_3

L47N_0

L46N_0

L35N_0

 

 

 

 

 

 

∇

 

 

 

 

 

 

 

 

 

 

 

J

INPUT

INPUT

INPUT

I/O

I/O

I/O

I/O

I/O

I/O

INPUT

I/O

I/O

INPUT

 

 

L20N_3

 

 

 

L24P_3

VREF_3

L20P_3

L19N_3

L19P_3

L13N_3

L10P_3

L01P_3

L01N_3

 

L43P_0

L39P_0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

INPUT

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GND

I/O

I/O

VCCAUX

 

 

L24N_3

L23N_3

L23P_3

L22N_3

L22P_3

L18P_3

L13P_3

L05N_3

L05P_3

L43N_0

L39N_0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

GND

VCCO_3

I/O

I/O

VCCAUX

GND

I/O

VCCO_3

I/O

I/O

GND

VCCINT

GND

 

 

L25N_3

L25P_3

L18N_3

L15N_3

L15P_3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

VCCINT

GND

VCCINT

 

 

L29N_3

 

 

L29P_3

L27N_3

L27P_3

L28P_3

L28N_3

L26N_3

L26P_3

L21N_3

L21P_3

 

 

 

VREF_3

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

I/O

I/O

 

I/O

I/O

I/O

I/O

 

I/O

 

 

 

 

 

N

GND

GND

L35P_3

VCCAUX

GND

VCCINT

VCCINT

 

L32P_3

L32N_3

 

L31P_3

L31N_3

L30N_3

L30P_3

TRDY2

 

Bank

 

I/O

L33N_3

I/O

I/O

 

I/O

I/O

I/O

I/O

I/O

 

 

 

 

 

 

 

 

 

 

 

LHCLK0

LHCLK1

 

LHCLK6

 

 

 

 

 

 

P

L33P_3

I/O

L34N_3

L34P_3

VCCO_3

L39N_3

L39P_3

L41P_3

L41N_3

L35N_3

VCCINT

GND

VCCINT

 

 

IRDY2

 

 

 

LHCLK2

LHCLK5

LHCLK4

 

LHCLK7

 

 

 

 

 

 

LHCLK3

 

 

 

 

 

 

 

 

 

 

R

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GND

VCCINT

GND

 

 

L36P_3

L43P_3

 

 

L36N_3

L37P_3

L37N_3

L40P_3

L40N_3

L45N_3

L45P_3

L43N_3

 

 

 

VREF_3

VREF_3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

GND

VCCO_3

I/O

I/O

I/O

GND

I/O

VCCO_3

I/O

I/O

VCCINT

GND

VCCINT

 

 

L38P_3

L38N_3

L42P_3

L51P_3

L48N_3

L48P_3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

U

I/O

I/O

INPUT

I/O

I/O

I/O

I/O

I/O

I/O

GND

I/O

VCCINT

GND

 

 

L44P_3

L44N_3

L46P_3

L42N_3

L49P_3

L51N_3

L56P_3

L56N_3

L61P_3

L13N_2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

I/O

I/O

GND

INPUT

I/O

I/O

I/O

I/O

VCCAUX

I/O

I/O

I/O

I/O

 

 

L47P_3

L47N_3

L46N_3

L49N_3

L59N_3

L59P_3

L61N_3

L09P_2

L13P_2

L16P_2

L20P_2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

INPUT

INPUT

I/O

I/O

VCCO_3

I/O

I/O

GND

I/O

I/O

VCCO_2

I/O

I/O

 

 

L50N_3

 

 

L50P_3

L52P_3

L52N_3

L63N_3

L63P_3

L05P_2

L09N_2

L16N_2

L20N_2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF_3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

I/O

INPUT

INPUT

I/O

I/O

I/O

INPUT

I/O

I/O

INPUT

I/O

I/O

 

 

Y

L54P_3

L54N_3

 

 

L02P_2

∇

∇

L17P_2

L25N_2

 

 

L53P_3

L53N_3

∇

∇

L57P_3

L57N_3

L05N_2

L12P_2

 

 

 

 

 

 

 

M2

 

 

 

 

RDWR_B

GCLK13

 

 

A

 

I/O

I/O

INPUT

INPUT

 

I/O

INPUT

INPUT

I/O

 

I/O

I/O

 

 

GND

L58P_3

L58N_3

GND

GND

 

 

A

L55P_3

L55N_3

∇

VREF_3

L02N_2

∇

VREF_2

L12N_2

L17N_2

L25P_2

 

 

 

 

CSO_B

 

VS2

GCLK12

 

 

 

 

 

∇

 

 

 

 

 

 

A

I/O

 

INPUT

INPUT

 

INPUT

I/O

 

I/O

INPUT

 

I/O

 

 

 

VCCO_3

L62P_3

L62N_3

VCCAUX

VCCO_2

VREF_2

VCCAUX

INPUT

 

 

B

 

 

L60P_3

 

∇

∇

 

VREF_2

L14N_2

 

L15P_2

∇

 

L21P_2

 

 

 

A

I/O

I/O

I/O

I/O

INPUT

I/O

INPUT

I/O

I/O

INPUT

I/O

I/O

INPUT

 

 

C

L60N_3

L64P_3

L64N_3

L01P_2

∇

L08P_2

∇

L14P_2

L15N_2

VREF_2

L23N_2

L21N_2

 

 

M1

 

 

 

A

I/O

I/O

GND

I/O

INPUT

I/O

I/O

GND

INPUT

INPUT

I/O

INPUT

GND

 

 

D

L65P_3

L65N_3

L01N_2

∇

L08N_2

L11P_2

L23P_2

VREF_2

 

 

 

M0

 

 

 

 

 

 

A

INPUT

INPUT

I/O

I/O

VCCO_2

I/O

I/O

I/O

I/O

I/O

VCCO_2

I/O

I/O

 

 

E

L66P_3

L66N_3

L06P_2

L07P_2

L10N_2

L11N_2

L18P_2

L19P_2

L22P_2

L24N_2

L26N_2

 

 

VREF_3

 

VS1

D7

 

D4

GCLK15

 

 

A

GND

INPUT

I/O

I/O

I/O

GND

INPUT

I/O

I/O

I/O

GND

I/O

I/O

 

 

F

∇

L06N_2

L07N_2

L10P_2

∇

L18N_2

L19N_2

L22N_2

L24P_2

L26P_2

 

 

 

 

VS0

D6

 

D5

GCLK14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bank 2

Figure 17: FG676 Package Footprint for XC3SD1800A FPGA (top view)

DS610-4 (v2.0) July 16, 2007

www.xilinx.com

81

Product Specification

Page 80 Page 82
Image 81
Page 80 Page 82
Contents DS610-1 v2.0 July 16 Product SpecificationDS610-2 v2.0 July 16 DS610-3 v2.0 July 16Data Sheet Features IntroductionSpartan-3A and Spartan-3A DSP Fpga Differences Architectural Overview ConfigurationCapabilities Introduction and Ordering InformationCS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A DCM519 227 XC3SD3400AOrdering Information Package MarkingStandard Packaging Pb-Free PackagingDate Version Revision Revision HistoryIntroduction and Ordering Information DS610-2 v2.0 July 16 Added Low-power options no changes to this moduleFunctional Description Symbol Description Conditions Min Max Units DC Electrical CharacteristicsAbsolute Maximum Ratings Absolute Maximum RatingsDC and Switching Characteristics Power Supply SpecificationsSupply Voltage Thresholds for Power-On Reset Symbol Description Min Max UnitsGeneral DC Characteristics for I/O Pins Symbol Description Test Conditions Min Typ Max Units= GND Typical2 Commercial Industrial Symbol Description Device Quiescent Supply Current CharacteristicsQuiescent Current Requirements Maximum2Single-Ended I/O Standards CCO for DriversAttribute Min Nom Max Attribute Test Logic Level Conditions CharacteristicsTest Logic Level Conditions Attribute Max MinDifferential I/O Standards Iostandard Attribute CCO for DriversMin Nom Max Min mV Nom mV Max mV Iostandard Attribute Min mV Typ mV Max mV Symbol Description Minimum Units Device DNA Identifier Memory CharacteristicsDevice DNA Data Retention, Read Endurance External Termination Requirements for Differential I/OSoftware Version Requirements Switching CharacteristicsSign Up for Alerts on Xilinx MySupport Spartan-3A DSP Speed File Version HistorySpartan-3A DSP v1.29 Speed Grade Designations Pin-to-Pin Clock-to-Output Times for the IOB Output Path TimingRate, without DCM At the Output pin. The DCM is not UseHold Times Ifddelayvalue =Device Min Units Setup Times Symbol Description ConditionsSet/Reset Pulse Width Speed GradeIoplid Lvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 Single-Ended StandardsPCI333 PCI663 Differential StandardsSet/Reset Times Asynchronous Output Enable/Disable TimesTiming for the IOB Three-State Path QuietIO QuietIO 27.67QuietIO 24.97 QuietIO 25.92Inputs Only LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25Timing Measurement Methodology Signal Standard Inputs OutputsTest Methods for Timing Measurement at I/Os InputsRT Ω DifferentialVicm + Simultaneously Switching Output Guidelines Equivalent VCCO/GND Pairs per BankDevice CS484 FG676 XC3SD1800A XC3SD3400A Signal Standard Top, Bottom Left, Right Package TypeCS484, FG676 Differential Standards Number of I/O Pairs or Channels QuietIO PCI333 PCI663Configurable Logic Block CLB Timing CLB Slicem TimingClock Timing Clock Buffer/Multiplexer Switching Characteristics CLB Shift Register Switching CharacteristicsClock Distribution Switching Characteristics Block RAM Timing Block RAM TimingClock Frequency Speed Grade Symbol Description Setup Times for the DSP48ASetup Times of Data Pins to the Pipeline Register Clock DSP48A TimingClock to Out from Input Register Clock to Output Pins Clock to Out from Pipeline Register Clock to Output PinsCombinatorial Delays from Input Pins to Output Pins Maximum FrequencyInput Clock Jitter Tolerance Delay Path Variation4 Delay-Locked Loop DLLDigital Clock Manager DCM Timing Recommended Operating Conditions for the DLLSpeed Grade Symbol Description Speed Grade Symbol Description Units Min Max Switching Characteristics for the DFSDigital Frequency Synthesizer DFS Recommended Operating Conditions for the DFSSwitching Characteristics for the PS in Variable Phase Mode Phase Shifter PSPhase Shifting Range Miscellaneous DCM TimingDnaport Interface Timing DNA Port TimingEntering Suspend Mode Exiting Suspend Mode Suspend Mode TimingEntering Suspend Mode Symbol Description Min Typ Max UnitsConfiguration and Jtag Timing General Configuration Power-On/Reconfigure TimingAll Speed Grades Symbol Description Device Min Max Units Master Mode Cclk Output Period by ConfigRate Option Setting Configuration Clock Cclk CharacteristicsCclk clock period by 11.2Slave Mode Cclk Input Low and High Time Master Mode Cclk Output Minimum Low and High TimeEquivalent Cclk clock frequency Cclk Low and High timeMaster Serial and Slave Serial Mode Timing Slave All Speed Grades Symbol DescriptionMin Max Units Clock-to-Output Times Slave Parallel Mode Timing Symbol Description Minimum Serial Peripheral Interface SPI Configuration TimingSymbol Description Requirement Units Symbol Description Minimum Maximum Units Byte Peripheral Interface BPI Configuration TimingSetup time on M20 mode pins before the rising edge of Initb Hold time on M20 mode pins after the rising edge of InitbParallel NOR Flash Prom output-enable time Symbol Description Requirement UnitsParallel NOR Flash Prom read access time Parallel NOR Flash Prom chip-select timeINTEST, EXTEST, Sample Ieee 1149.1/1553 Jtag Test Access Port TimingDSP48A timing in and Table Diffhstli and Diffhstliii to , , and . Updated Tmds DCDC and Switching Characteristics Types of Pins on Spartan-3A DSP FPGAs Pin TypesType/Color Description Pin Names in Type Code Pinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Package Pins by TypePower and Ground Supply Pins by Package Maximum User I/O by PackagePackage Thermal Characteristics Spartan-3A DSP Package Thermal CharacteristicsPinout Descriptions Pinout Table CS484 484-Ball Chip-Scale Ball Grid ArraySpartan-3A DSP CS484 Pinout Bank Pin Name CS484 Type BallPinout Descriptions Spartan-3A DSP CS484 Pinout AA3 Dual VCCO1AA4 AA6 InputVCCO2 VCCO2 AA5 Vcco AA9VCCO2 Vcco AA1 VrefVCCO3 Vcco GND AA7GND AB1 Vccaux TCK Vccaux Progb Config DoneJtag Vccaux TMS Jtag TDOFootprint Migration Differences User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the CS484 Package User I/Os Per Bank for the XC3SD3400A in the CS484 PackageLeft Half of Package top view CS484 FootprintRight Half of CS484 Package top view Pinout Table FG676 676-Ball Fine-Pitch Ball Grid ArraySpartan-3A DSP FG676 Pinout for Spartan-3A DSP FG676 Pinout for XC3SD1800A FpgaIOL26N0/GCLK7 IOL26P0/GCLK6IOL30P1/RHCLK0 IOL30N1/RHCLK1IOL33P1/RHCLK4 IOL31P1/RHCLK2IOL27P2/GCLK0 IOL17P2/RDWRBAF4 AF3AF5 AF7 InputAB9 IP2/VREF2 AB6 VrefIOL30N2/MOSI/CSIB IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 VrefIOL34N3/LHCLK5 IOL33P3/LHCLK2IOL34P3/LHCLK4 IOL35N3/LHCLK7AE2 Vref AE1 InputAD1 AD2GND AF1 AF6 Vccaux Progb Config TDI Jtag TDOGND AD3 AD8 GND AA1 AA6User I/Os Per Bank for the XC3SD1800A in the FG676 Package User I/Os by BankTop 128 Right 519 314FG676 Package Footprint for XC3SD1800A Fpga top view FG676 FootprintTDO Bank XC3SD3400A Pin Name FG676 Type Ball Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaIOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 IOL01P0 G20IP1/VREF1 VCCO0 Vcco IOL01P1/HDCIOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16 IOL34P1/IRDY1/RHCLK6IOL05N1 AC25 IOL06P1 T25IOL12P2 Y10 IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 VCCO2 AF7 Vcco AE5IOL53P3 IOL53N3 IP3 IOL36N3 IOL37P3IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IP3/VREF3 Vref IOL10N3 IOL03N3 IP3AA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND GND AC5 AC7 GND AD3 AD5 AD8GND AB3 GND AA1 AA4 AA6Vccint AA8 Vccaux AF2 AB4 AB5User I/Os Per Bank for the XC3SD3400A in the FG676 Package Vref are on Input pinsTop 111 Right Bottom 112 LeftPinout Descriptions FG676 Package Footprint for XC3SD3400A Fpga top viewVCCO0 VREF1 VREF1 FG676 Footprint Migration DifferencesPinout Descriptions FG676 Footprint Migration Differences Migration RecommendationsFpga and XC3SD3400A Fpga . Minor edits SPARTAN-3A DSPPinout Descriptions
Top Page Image Contents