Xilinx DS610 VCCO1, AA3 Dual, AA4, AA6 Input, AA8, IOL18N2/GCLK3, IOL22P2/AWAKE, AB3 Dual, AB4

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Pinout Descriptions

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Table 60: Spartan-3A DSP CS484 Pinout (Continued)

	Bank	Pin Name	CS484	Type
	Bank	Pin Name	Ball	Type
			Ball
	1	IO_L03N_1/A1	V20	DUAL

	1	IP_L08P_1	V22	INPUT

	1	IO_L03P_1/A0	W19	DUAL

	1	IP_L04N_1/VREF_1	W20	VREF

	1	IP_L04P_1	W21	INPUT

	1	IO_L06P_1	W22	I/O

	1	IO_L02P_1/LDC1	Y21	DUAL

	1	IO_L06N_1	Y22	I/O

	1	VCCO_1	E21	VCCO

	1	VCCO_1	J18	VCCO

	1	VCCO_1	K21	VCCO

	1	VCCO_1	P18	VCCO

	1	VCCO_1	P21	VCCO

	1	VCCO_1	V21	VCCO

	2	IO_L01P_2/M1	AA3	DUAL

	2	IO_L04N_2	AA4	I/O

	2	IP_2	AA6	INPUT

	2	IO_L08N_2	AA8	I/O

	2	IO_L12N_2/D6	AA10	DUAL

	2	IO_L16P_2/GCLK14	AA12	GCLK

	2	IO_L18N_2/GCLK3	AA14	GCLK

	2	IO_L19P_2	AA15	I/O

	2	IO_L22P_2/AWAKE	AA17	PWRMGMT

	2	IO_L27N_2	AA19	I/O

	2	IO_L30P_2	AA20	I/O

	2	IP_2/VREF_2	AB2	VREF

	2	IO_L01N_2/M0	AB3	DUAL

	2	IO_L04P_2	AB4	I/O

	2	IO_L05P_2	AB5	I/O

	2	IO_L05N_2	AB6	I/O

	2	IO_L08P_2	AB7	I/O

	2	IO_L09P_2/VS1	AB8	DUAL

	2	IO_L09N_2/VS0	AB9	DUAL

	2	IO_L12P_2/D7	AB10	DUAL

	2	IP_2/VREF_2	AB11	VREF

	2	IO_L16N_2/GCLK15	AB12	GCLK

	2	IO_L18P_2/GCLK2	AB13	GCLK

	2	IO_L1N_2	AB14	I/O

	2	IP_2	AB15	INPUT

	2	IO_L22N_2/DOUT	AB16	DUAL

	2	IO_L23P_2	AB17	I/O

	2	IO_L23N_2	AB18	I/O

Table 60: Spartan-3A DSP CS484 Pinout (Continued)

	Bank	Pin Name	CS484	Type
	Bank	Pin Name	Ball	Type
			Ball
	2	IO_L27P_2	AB19	I/O

	2	IO_L30N_2	AB20	I/O

	2	IO_L02N_2/CSO_B	U7	DUAL

	2	IO_L11N_2	U8	I/O

	2	IO_L10N_2	U9	I/O

	2	IO_L14N_2/D4	U10	DUAL

	2	IO_L17P_2/GCLK0	U12	GCLK

	2	IO_L20P_2	U13	I/O

	2	IO_L25P_2	U14	I/O

	2	IO_L25N_2	U15	I/O

	2	IO_L28P_2	U16	I/O

	2	IO_L02P_2/M2	V6	DUAL

	2	IO_L11P_2	V7	I/O

	2	IO_L06N_2	V8	I/O

	2	IO_L10P_2	V10	I/O

	2	IO_L14P_2/D5	V11	DUAL

	2	IO_L17N_2/GCLK1	V12	GCLK

	2	IO_L20N_2/MOSI/CSI_B	V13	DUAL

	2	IP_2/VREF_2	V15	VREF

	2	IO_L28N_2	V16	I/O

	2	IO_L31N_2/CCLK	V17	DUAL

	2	IP_2/VREF_2	W4	VREF

	2	IO_L03P_2	W5	I/O

	2	IO_L07N_2/VS2	W6	DUAL

	2	IO_L06P_2	W8	I/O

	2	IP_2/VREF_2	W9	VREF

	2	IP_2	W10	INPUT

	2	IP_2/VREF_2	W13	VREF

	2	IO_L21N_2	W14	I/O

	2	IO_L24P_2/INIT_B	W15	DUAL

	2	IO_L31P_2/D0/DIN/MISO	W17	DUAL

	2	IP_2/VREF_2	W18	VREF

	2	IO_L03N_2	Y4	I/O

	2	IO_L07P_2/RDWR_B	Y5	DUAL

	2	IP_2	Y6	INPUT

	2	IP_2	Y7	INPUT

	2	IO_L13P_2	Y8	I/O

	2	IO_L13N_2	Y9	I/O

	2	IO_L15N_2/GCLK13	Y10	GCLK

	2	IO_L15P_2/GCLK12	Y11	GCLK

	2	IP_2	Y12	INPUT

	2	IO_L21P_2	Y13	I/O

64	www.xilinx.com	DS610-4 (v2.0) July 16, 2007
		Product Specification

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Contents Product Specification DS610-1 v2.0 July 16DS610-2 v2.0 July 16 DS610-3 v2.0 July 16Data Sheet Introduction FeaturesSpartan-3A and Spartan-3A DSP Fpga Differences Configuration Architectural OverviewCapabilities Introduction and Ordering InformationDCM CS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A519 227 XC3SD3400APackage Marking Ordering InformationStandard Packaging Pb-Free PackagingRevision History Date Version RevisionIntroduction and Ordering Information Added Low-power options no changes to this module DS610-2 v2.0 July 16Functional Description DC Electrical Characteristics Symbol Description Conditions Min Max UnitsAbsolute Maximum Ratings Absolute Maximum RatingsPower Supply Specifications DC and Switching CharacteristicsSupply Voltage Thresholds for Power-On Reset Symbol Description Min Max UnitsSymbol Description Test Conditions Min Typ Max Units General DC Characteristics for I/O Pins= GND Quiescent Supply Current Characteristics Typical2 Commercial Industrial Symbol Description DeviceQuiescent Current Requirements Maximum2CCO for Drivers Single-Ended I/O StandardsAttribute Min Nom Max Test Logic Level Conditions Characteristics AttributeTest Logic Level Conditions Attribute Max MinIostandard Attribute CCO for Drivers Differential I/O StandardsMin Nom Max Min mV Nom mV Max mV Iostandard Attribute Min mV Typ mV Max mV Device DNA Identifier Memory Characteristics Symbol Description Minimum UnitsDevice DNA Data Retention, Read Endurance External Termination Requirements for Differential I/OSwitching Characteristics Software Version RequirementsSpartan-3A DSP Speed File Version History Sign Up for Alerts on Xilinx MySupportSpartan-3A DSP v1.29 Speed Grade Designations Timing Pin-to-Pin Clock-to-Output Times for the IOB Output PathRate, without DCM At the Output pin. The DCM is not UseIfddelayvalue = Hold TimesSymbol Description Conditions Device Min Units Setup TimesSet/Reset Pulse Width Speed GradeIoplid Single-Ended Standards Lvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12PCI333 PCI663 Differential StandardsAsynchronous Output Enable/Disable Times Set/Reset TimesTiming for the IOB Three-State Path QuietIO 27.67 QuietIOQuietIO 25.92 QuietIO 24.97LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25 Inputs OnlySignal Standard Inputs Outputs Timing Measurement MethodologyTest Methods for Timing Measurement at I/Os InputsDifferential RT ΩVicm + Equivalent VCCO/GND Pairs per Bank Simultaneously Switching Output GuidelinesDevice CS484 FG676 XC3SD1800A XC3SD3400A Package Type Signal Standard Top, Bottom Left, RightCS484, FG676 QuietIO PCI333 PCI663 Differential Standards Number of I/O Pairs or ChannelsCLB Slicem Timing Configurable Logic Block CLB TimingClock Timing CLB Shift Register Switching Characteristics Clock Buffer/Multiplexer Switching CharacteristicsClock Distribution Switching Characteristics Block RAM Timing Block RAM TimingClock Frequency Setup Times for the DSP48A Speed Grade Symbol DescriptionSetup Times of Data Pins to the Pipeline Register Clock DSP48A TimingClock to Out from Pipeline Register Clock to Output Pins Clock to Out from Input Register Clock to Output PinsCombinatorial Delays from Input Pins to Output Pins Maximum FrequencyDelay-Locked Loop DLL Input Clock Jitter Tolerance Delay Path Variation4Digital Clock Manager DCM Timing Recommended Operating Conditions for the DLLSpeed Grade Symbol Description Switching Characteristics for the DFS Speed Grade Symbol Description Units Min MaxDigital Frequency Synthesizer DFS Recommended Operating Conditions for the DFSPhase Shifter PS Switching Characteristics for the PS in Variable Phase ModePhase Shifting Range Miscellaneous DCM TimingDNA Port Timing Dnaport Interface TimingSuspend Mode Timing Entering Suspend Mode Exiting Suspend ModeEntering Suspend Mode Symbol Description Min Typ Max UnitsGeneral Configuration Power-On/Reconfigure Timing Configuration and Jtag TimingAll Speed Grades Symbol Description Device Min Max Units Configuration Clock Cclk Characteristics Master Mode Cclk Output Period by ConfigRate Option SettingCclk clock period by 11.2Master Mode Cclk Output Minimum Low and High Time Slave Mode Cclk Input Low and High TimeEquivalent Cclk clock frequency Cclk Low and High timeSlave All Speed Grades Symbol Description Master Serial and Slave Serial Mode TimingMin Max Units Clock-to-Output Times Slave Parallel Mode Timing Serial Peripheral Interface SPI Configuration Timing Symbol Description MinimumSymbol Description Requirement Units Byte Peripheral Interface BPI Configuration Timing Symbol Description Minimum Maximum UnitsSetup time on M20 mode pins before the rising edge of Initb Hold time on M20 mode pins after the rising edge of InitbSymbol Description Requirement Units Parallel NOR Flash Prom output-enable timeParallel NOR Flash Prom read access time Parallel NOR Flash Prom chip-select timeIeee 1149.1/1553 Jtag Test Access Port Timing INTEST, EXTEST, SampleDiffhstli and Diffhstliii to , , and . Updated Tmds DC DSP48A timing in and TableDC and Switching Characteristics Pin Types Types of Pins on Spartan-3A DSP FPGAsType/Color Description Pin Names in Type Code Package Pins by Type Pinout Descriptions Types of Pins on Spartan-3A DSP FPGAsPower and Ground Supply Pins by Package Maximum User I/O by Package Spartan-3A DSP Package Thermal Characteristics Package Thermal Characteristics Pinout Descriptions CS484 484-Ball Chip-Scale Ball Grid Array Pinout TableSpartan-3A DSP CS484 Pinout Bank Pin Name CS484 Type BallPinout Descriptions Spartan-3A DSP CS484 Pinout VCCO1 AA3 DualAA4 AA6 InputVCCO2 AA5 Vcco AA9 VCCO2VCCO2 Vcco AA1 VrefGND AA7 VCCO3 VccoGND AB1 Vccaux Progb Config Done Vccaux TCKJtag Vccaux TMS Jtag TDOUser I/Os by Bank Footprint Migration DifferencesUser I/Os Per Bank for the XC3SD1800A in the CS484 Package User I/Os Per Bank for the XC3SD3400A in the CS484 PackageCS484 Footprint Left Half of Package top viewRight Half of CS484 Package top view FG676 676-Ball Fine-Pitch Ball Grid Array Pinout TableSpartan-3A DSP FG676 Pinout for Spartan-3A DSP FG676 Pinout for XC3SD1800A FpgaIOL26P0/GCLK6 IOL26N0/GCLK7IOL30N1/RHCLK1 IOL30P1/RHCLK0IOL33P1/RHCLK4 IOL31P1/RHCLK2IOL17P2/RDWRB IOL27P2/GCLK0AF3 AF4AF5 AF7 InputIP2/VREF2 AB6 Vref AB9IOL30N2/MOSI/CSIB IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 VrefIOL33P3/LHCLK2 IOL34N3/LHCLK5IOL34P3/LHCLK4 IOL35N3/LHCLK7AE1 Input AE2 VrefAD1 AD2Vccaux Progb Config TDI Jtag TDO GND AF1 AF6GND AD3 AD8 GND AA1 AA6User I/Os by Bank User I/Os Per Bank for the XC3SD1800A in the FG676 PackageTop 128 Right 519 314FG676 Footprint FG676 Package Footprint for XC3SD1800A Fpga top viewTDO Spartan-3A DSP FG676 Pinout for XC3SD3400A Fpga Bank XC3SD3400A Pin Name FG676 Type BallIOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 IOL01P0 G20VCCO0 Vcco IOL01P1/HDC IP1/VREF1IOL34P1/IRDY1/RHCLK6 IOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16T25 IOL05N1 AC25 IOL06P1IOL12P2 Y10 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13 IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 VCCO2 AF7 Vcco AE5IOL36N3 IOL37P3 IOL53P3 IOL53N3 IP3IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IOL10N3 IOL03N3 IP3 IP3/VREF3 VrefAA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND GND AD3 AD5 AD8 GND AC5 AC7GND AB3 GND AA1 AA4 AA6Vccaux AF2 AB4 AB5 Vccint AA8Vref are on Input pins User I/Os Per Bank for the XC3SD3400A in the FG676 PackageTop 111 Right Bottom 112 LeftFG676 Package Footprint for XC3SD3400A Fpga top view Pinout DescriptionsVCCO0 VREF1 FG676 Footprint Migration Differences VREF1Migration Recommendations Pinout Descriptions FG676 Footprint Migration DifferencesSPARTAN-3A DSP Fpga and XC3SD3400A Fpga . Minor editsPinout Descriptions