Xilinx DS610 Timing Measurement Methodology, Test Methods for Timing Measurement at I/Os, Inputs

Page 31

R

DC and Switching Characteristics

Timing Measurement Methodology

When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions. Table 25 lists the conditions to use for each standard.

open connection, and VT is set to zero. The same measurement point (VM) that was used at the Input is also used at the Output.

The method for measuring Input timing is as follows: A signal that swings between a Low logic level of VL and a High logic level of VH is applied to the Input under test. Some standards also require the application of a bias

voltage to the VREF pins of a given bank to properly set the input-switching threshold. The measurement point of the

Input signal (VM) is commonly located halfway between VL and VH.

VT (VREF)

FPGA Output

RT (RREF)

VM (VMEAS)

CL (CREF)

The Output test setup is shown in Figure 8. A termination voltage VT is applied to the termination resistor RT, the other end of which is connected to the Output. For each standard, RT and VT generally take on the standard values recommended for minimizing signal reflections. If the standard does not ordinarily use terminations (for example, LVCMOS, LVTTL), then RT is set to 1MΩ to indicate an

Table 25: Test Methods for Timing Measurement at I/Os

DS312-3_04_102406

Notes:

1.The names shown in parentheses are used in the IBIS file.

Figure 8: Output Test Setup

 

 

 

 

 

 

 

 

 

 

 

Inputs and

Signal Standard

 

 

Inputs

 

 

 

Outputs

Outputs

 

 

 

 

 

 

 

 

 

(IOSTANDARD)

VREF (V)

VL (V)

 

VH (V)

RT (Ω)

 

VT (V)

VM (V)

Single-Ended

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LVTTL

 

 

-

0

 

3.3

1M

 

0

1.4

 

 

 

 

 

 

 

 

 

 

 

LVCMOS33

 

 

-

0

 

3.3

1M

 

0

1.65

 

 

 

 

 

 

 

 

 

 

 

LVCMOS25

 

 

-

0

 

2.5

1M

 

0

1.25

 

 

 

 

 

 

 

 

 

 

 

LVCMOS18

 

 

-

0

 

1.8

1M

 

0

0.9

 

 

 

 

 

 

 

 

 

 

 

LVCMOS15

 

 

-

0

 

1.5

1M

 

0

0.75

 

 

 

 

 

 

 

 

 

 

 

LVCMOS12

 

 

-

0

 

1.2

1M

 

0

0.6

 

 

 

 

 

 

 

 

 

 

 

PCI33_3

 

Rising

-

Note 3

 

Note 3

25

 

0

0.94

 

 

 

 

 

 

 

 

 

 

 

 

 

Falling

 

 

 

 

25

 

3.3

2.03

 

 

 

 

 

 

 

 

 

 

 

PCI66_3

 

Rising

-

Note 3

 

Note 3

25

 

0

0.94

 

 

 

 

 

 

 

 

 

 

 

 

 

Falling

 

 

 

 

25

 

3.3

2.03

 

 

 

 

 

 

 

 

 

 

 

PCIX

 

Rising

-

Note 3

 

Note 3

25

 

0

0.94

 

 

 

 

 

 

 

 

 

 

 

 

 

Falling

 

 

 

 

25

 

3.3

2.03

 

 

 

 

 

 

 

 

 

 

 

 

HSTL_I

 

 

0.75

VREF – 0.5

 

VREF + 0.5

50

 

0.75

VREF

HSTL_III

 

 

0.9

VREF – 0.5

 

VREF + 0.5

50

 

1.5

VREF

HSTL_I_18

 

 

0.9

VREF – 0.5

 

VREF + 0.5

50

 

0.9

VREF

HSTL_II_18

 

 

0.9

VREF – 0.5

 

VREF + 0.5

25

 

0.9

VREF

HSTL_III_18

 

 

1.1

VREF – 0.5

 

VREF + 0.5

50

 

1.8

VREF

SSTL18_I

 

 

0.9

VREF – 0.5

 

VREF + 0.5

50

 

0.9

VREF

SSTL18_II

 

 

0.9

VREF – 0.5

 

VREF + 0.5

25

 

0.9

VREF

SSTL2_I

 

 

1.25

VREF – 0.75

 

VREF + 0.75

50

 

1.25

VREF

SSTL2_II

 

 

1.25

VREF – 0.75

 

VREF + 0.75

25

 

1.25

VREF

 

 

 

 

 

 

 

 

 

 

 

 

DS610-3 (v2.0) July 16, 2007

 

 

www.xilinx.com

 

 

 

31

Product Specification

 

 

 

 

 

 

 

 

Page 30 Page 32
Image 31
Page 30 Page 32
Contents DS610-3 v2.0 July 16 Product SpecificationDS610-1 v2.0 July 16 DS610-2 v2.0 July 16Data Sheet Introduction FeaturesSpartan-3A and Spartan-3A DSP Fpga Differences Introduction and Ordering Information ConfigurationArchitectural Overview CapabilitiesXC3SD3400A DCMCS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A 519 227Pb-Free Packaging Package MarkingOrdering Information Standard PackagingDate Version Revision Revision HistoryIntroduction and Ordering Information DS610-2 v2.0 July 16 Added Low-power options no changes to this moduleFunctional Description Absolute Maximum Ratings DC Electrical CharacteristicsSymbol Description Conditions Min Max Units Absolute Maximum RatingsSymbol Description Min Max Units Power Supply SpecificationsDC and Switching Characteristics Supply Voltage Thresholds for Power-On ResetSymbol Description Test Conditions Min Typ Max Units General DC Characteristics for I/O Pins= GND Maximum2 Quiescent Supply Current CharacteristicsTypical2 Commercial Industrial Symbol Description Device Quiescent Current RequirementsCCO for Drivers Single-Ended I/O StandardsAttribute Min Nom Max Attribute Max Min Test Logic Level Conditions CharacteristicsAttribute Test Logic Level ConditionsIostandard Attribute CCO for Drivers Differential I/O StandardsMin Nom Max Min mV Nom mV Max mV Iostandard Attribute Min mV Typ mV Max mV External Termination Requirements for Differential I/O Device DNA Identifier Memory CharacteristicsSymbol Description Minimum Units Device DNA Data Retention, Read EnduranceSoftware Version Requirements Switching CharacteristicsSpartan-3A DSP Speed File Version History Sign Up for Alerts on Xilinx MySupportSpartan-3A DSP v1.29 Speed Grade Designations At the Output pin. The DCM is not Use TimingPin-to-Pin Clock-to-Output Times for the IOB Output Path Rate, without DCMHold Times Ifddelayvalue =Speed Grade Symbol Description ConditionsDevice Min Units Setup Times Set/Reset Pulse WidthIoplid Differential Standards Single-Ended StandardsLvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI333 PCI663Asynchronous Output Enable/Disable Times Set/Reset TimesTiming for the IOB Three-State Path QuietIO QuietIO 27.67QuietIO 24.97 QuietIO 25.92Inputs Only LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25Inputs Signal Standard Inputs OutputsTiming Measurement Methodology Test Methods for Timing Measurement at I/OsDifferential RT ΩVicm + Equivalent VCCO/GND Pairs per Bank Simultaneously Switching Output GuidelinesDevice CS484 FG676 XC3SD1800A XC3SD3400A Package Type Signal Standard Top, Bottom Left, RightCS484, FG676 Differential Standards Number of I/O Pairs or Channels QuietIO PCI333 PCI663CLB Slicem Timing Configurable Logic Block CLB TimingClock Timing CLB Shift Register Switching Characteristics Clock Buffer/Multiplexer Switching CharacteristicsClock Distribution Switching Characteristics Block RAM Timing Block RAM TimingClock Frequency DSP48A Timing Setup Times for the DSP48ASpeed Grade Symbol Description Setup Times of Data Pins to the Pipeline Register ClockMaximum Frequency Clock to Out from Pipeline Register Clock to Output PinsClock to Out from Input Register Clock to Output Pins Combinatorial Delays from Input Pins to Output PinsRecommended Operating Conditions for the DLL Delay-Locked Loop DLLInput Clock Jitter Tolerance Delay Path Variation4 Digital Clock Manager DCM TimingSpeed Grade Symbol Description Recommended Operating Conditions for the DFS Switching Characteristics for the DFSSpeed Grade Symbol Description Units Min Max Digital Frequency Synthesizer DFSMiscellaneous DCM Timing Phase Shifter PSSwitching Characteristics for the PS in Variable Phase Mode Phase Shifting RangeDnaport Interface Timing DNA Port TimingSymbol Description Min Typ Max Units Suspend Mode TimingEntering Suspend Mode Exiting Suspend Mode Entering Suspend ModeGeneral Configuration Power-On/Reconfigure Timing Configuration and Jtag TimingAll Speed Grades Symbol Description Device Min Max Units 11.2 Configuration Clock Cclk CharacteristicsMaster Mode Cclk Output Period by ConfigRate Option Setting Cclk clock period byCclk Low and High time Master Mode Cclk Output Minimum Low and High TimeSlave Mode Cclk Input Low and High Time Equivalent Cclk clock frequencySlave All Speed Grades Symbol Description Master Serial and Slave Serial Mode TimingMin Max Units Clock-to-Output Times Slave Parallel Mode Timing Symbol Description Minimum Serial Peripheral Interface SPI Configuration TimingSymbol Description Requirement Units Hold time on M20 mode pins after the rising edge of Initb Byte Peripheral Interface BPI Configuration TimingSymbol Description Minimum Maximum Units Setup time on M20 mode pins before the rising edge of InitbParallel NOR Flash Prom chip-select time Symbol Description Requirement UnitsParallel NOR Flash Prom output-enable time Parallel NOR Flash Prom read access timeINTEST, EXTEST, Sample Ieee 1149.1/1553 Jtag Test Access Port TimingDSP48A timing in and Table Diffhstli and Diffhstliii to , , and . Updated Tmds DCDC and Switching Characteristics Pin Types Types of Pins on Spartan-3A DSP FPGAsType/Color Description Pin Names in Type Code Maximum User I/O by Package Package Pins by TypePinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Power and Ground Supply Pins by PackageSpartan-3A DSP Package Thermal Characteristics Package Thermal CharacteristicsPinout Descriptions Bank Pin Name CS484 Type Ball CS484 484-Ball Chip-Scale Ball Grid ArrayPinout Table Spartan-3A DSP CS484 PinoutPinout Descriptions Spartan-3A DSP CS484 Pinout AA6 Input VCCO1AA3 Dual AA4AA1 Vref VCCO2 AA5 Vcco AA9VCCO2 VCCO2 VccoGND AA7 VCCO3 VccoGND AB1 Vccaux TMS Jtag TDO Vccaux Progb Config DoneVccaux TCK JtagUser I/Os Per Bank for the XC3SD3400A in the CS484 Package User I/Os by BankFootprint Migration Differences User I/Os Per Bank for the XC3SD1800A in the CS484 PackageLeft Half of Package top view CS484 FootprintRight Half of CS484 Package top view Spartan-3A DSP FG676 Pinout for XC3SD1800A Fpga FG676 676-Ball Fine-Pitch Ball Grid ArrayPinout Table Spartan-3A DSP FG676 Pinout forIOL26N0/GCLK7 IOL26P0/GCLK6IOL31P1/RHCLK2 IOL30N1/RHCLK1IOL30P1/RHCLK0 IOL33P1/RHCLK4IOL27P2/GCLK0 IOL17P2/RDWRBAF7 Input AF3AF4 AF5IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 Vref IP2/VREF2 AB6 VrefAB9 IOL30N2/MOSI/CSIBIOL35N3/LHCLK7 IOL33P3/LHCLK2IOL34N3/LHCLK5 IOL34P3/LHCLK4AD2 AE1 InputAE2 Vref AD1GND AA1 AA6 Vccaux Progb Config TDI Jtag TDOGND AF1 AF6 GND AD3 AD8519 314 User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the FG676 Package Top 128 RightFG676 Package Footprint for XC3SD1800A Fpga top view FG676 FootprintTDO IOL01P0 G20 Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaBank XC3SD3400A Pin Name FG676 Type Ball IOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0IP1/VREF1 VCCO0 Vcco IOL01P1/HDCIOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16 IOL34P1/IRDY1/RHCLK6T25 IOL05N1 AC25 IOL06P1IOL12P2 Y10 VCCO2 AF7 Vcco AE5 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22IOL36N3 IOL37P3 IOL53P3 IOL53N3 IP3IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IOL10N3 IOL03N3 IP3 IP3/VREF3 VrefAA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND GND AA1 AA4 AA6 GND AD3 AD5 AD8GND AC5 AC7 GND AB3Vccint AA8 Vccaux AF2 AB4 AB5Bottom 112 Left Vref are on Input pinsUser I/Os Per Bank for the XC3SD3400A in the FG676 Package Top 111 RightPinout Descriptions FG676 Package Footprint for XC3SD3400A Fpga top viewVCCO0 VREF1 VREF1 FG676 Footprint Migration DifferencesPinout Descriptions FG676 Footprint Migration Differences Migration RecommendationsFpga and XC3SD3400A Fpga . Minor edits SPARTAN-3A DSPPinout Descriptions
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