Xilinx DS610 manual Introduction, Features, Spartan-3A and Spartan-3A DSP Fpga Differences

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Summary of Spartan-3A DSP FPGA Attributes

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Spartan-3A DSP FPGA Family: Introduction and Ordering Information

DS610-1 (v2.0) July 16, 2007

Product Specification

 

 

Introduction

The Spartan™-3A DSP family of Field-Programmable Gate Arrays (FPGAs) solves the design challenges in most high-volume, cost-sensitive, high-performance DSP applications. The two-member family offers densities ranging from 1.8 to 3.4 million system gates, as shown in Table 1.

The Spartan-3A DSP family builds on the success of the Spartan-3A FPGA family by increasing the amount of memory per logic and adding XtremeDSP™ DSP48A slices. New features improve system performance and reduce the cost of configuration. These Spartan-3A DSP FPGA enhancements, combined with proven 90 nm process technology, deliver more functionality and bandwidth per dollar than ever before, setting the new standard in the programmable logic and DSP processing industry.

Spartan-3A and Spartan-3A DSP FPGA Differences

The Spartan-3A DSP FPGAs extend and enhance the Spartan-3A FPGA family. The XC3SD1800A and the XC3SD3400A devices are tailored for DSP applications and have additional block RAM and XtremeDSP DSP48A slices. The XtremeDSP DSP48A slices replace the 18x18 multipliers found in the Spartan-3A devices and are based on the DSP48 blocks found in the Virtex™-4 devices. The block RAMs are also enhanced to run faster by adding an output register. Both the block RAM and DSP48A slices in the Spartan-3A DSP devices run at 250 MHz in the lowest cost, standard -4 speed grade.

Because of their exceptional DSP price/performance ratio, Spartan-3A DSP FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment.

The Spartan-3A DSP family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.

Features

•Very low cost, high-performance DSP solution for high-volume, cost-conscious applications

•250 MHz XtremeDSP DSP48A Slices

♦ Dedicated 18-bit by 18-bit multiplier

♦Available pipeline stages for enhanced performance of at least 250 MHz in the standard -4 speed grade

♦48-bit accumulator for multiply-accumulate (MAC) operation

♦Integration added for complex multiply or multiply-add operation

♦Integrated 18-bit pre-adder

♦Optional cascaded Multiply or MAC

•Hierarchical SelectRAM™ memory architecture

♦Up to 2268 Kbits of fast block RAM with byte write enables for processor applications

♦Up to 373 Kbits of efficient distributed RAM

♦Registered outputs on the block RAM with operation of at least 280 MHz in the standard -4 speed grade

•Dual-range VCCAUX supply simplifies 3.3V-only design

•Suspend, Hibernate modes reduce system power

•Low-power option reduces quiescent current

•Multi-voltage, multi-standard SelectIO™ interface pins

♦Up to 519 I/O pins or 227 differential signal pairs

♦LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O

♦3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

♦Selectable output drive, up to 24 mA per pin

♦QUIETIO standard reduces I/O switching noise

♦Full 3.3V ± 10% compatibility and hot swap compliance

♦622+ Mb/s data transfer rate per differential I/O

♦LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with integrated differential termination resistors

♦Enhanced Double Data Rate (DDR) support

♦DDR/DDR2 SDRAM support up to 333 Mb/s

♦Fully compliant 32-/64-bit, 33/66 MHz PCI support

•Abundant, flexible logic resources

♦Densities up to 53712 logic cells, including optional shift register

♦Efficient wide multiplexers, wide logic

♦Fast look-ahead carry logic

♦IEEE 1149.1/1532 JTAG programming/debug port

•Eight Digital Clock Managers (DCMs)

♦Clock skew elimination (delay locked loop)

♦Frequency synthesis, multiplication, division

♦High-resolution phase shifting

♦Wide frequency range (5 MHz to over 320 MHz)

•Eight low-skew global clock networks, eight additional clocks per half device, plus abundant low-skew routing

•Configuration interface to industry-standard PROMs

♦Low-cost, space-saving SPI serial Flash PROM

♦x8 or x8/x16 parallel NOR Flash PROM

♦Low-cost Xilinx Platform Flash with JTAG

♦Unique Device DNA identifier for design authentication

♦Load multiple bitstreams under FPGA control

•MicroBlaze™ and PicoBlaze™ embedded processor cores

•BGA and CSP packaging with Pb-free options

♦Common footprints support easy density migration

Table 1:

Device

 

 

CLB Array (One CLB = Four Slices)

Distributed

System

Equivalent

 

 

Total

Total

RAM

Gates

Logic Cells

Rows

Columns

CLBs

Slices

Bits(1)

Block

RAM

Bits(1)

 

 

 

Maximum

 

 

Maximum

Differential

DSP48As

DCMs

User I/O

I/O Pairs

 

 

 

 

XC3SD1800A

1800K

37,440

88

48

4160

16640

260K

1512K

84

8

519

227

XC3SD3400A

3400K

53,712

104

58

5968

23872

373K

2268K

126

8

469

213

Notes: 1. By convention, one Kb is equivalent to 1,024 bits.

© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.

All other trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS610-1 (v2.0) July 16, 2007

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Product Specification

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Contents DS610-3 v2.0 July 16 Product SpecificationDS610-1 v2.0 July 16 DS610-2 v2.0 July 16Data Sheet Features IntroductionSpartan-3A and Spartan-3A DSP Fpga Differences Introduction and Ordering Information ConfigurationArchitectural Overview CapabilitiesXC3SD3400A DCMCS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A 519 227Pb-Free Packaging Package MarkingOrdering Information Standard PackagingDate Version Revision Revision HistoryIntroduction and Ordering Information DS610-2 v2.0 July 16 Added Low-power options no changes to this moduleFunctional Description Absolute Maximum Ratings DC Electrical CharacteristicsSymbol Description Conditions Min Max Units Absolute Maximum RatingsSymbol Description Min Max Units Power Supply SpecificationsDC and Switching Characteristics Supply Voltage Thresholds for Power-On ResetGeneral DC Characteristics for I/O Pins Symbol Description Test Conditions Min Typ Max Units= GND Maximum2 Quiescent Supply Current CharacteristicsTypical2 Commercial Industrial Symbol Description Device Quiescent Current RequirementsSingle-Ended I/O Standards CCO for DriversAttribute Min Nom Max Attribute Max Min Test Logic Level Conditions CharacteristicsAttribute Test Logic Level ConditionsDifferential I/O Standards Iostandard Attribute CCO for DriversMin Nom Max Min mV Nom mV Max mV Iostandard Attribute Min mV Typ mV Max mV External Termination Requirements for Differential I/O Device DNA Identifier Memory CharacteristicsSymbol Description Minimum Units Device DNA Data Retention, Read EnduranceSoftware Version Requirements Switching CharacteristicsSign Up for Alerts on Xilinx MySupport Spartan-3A DSP Speed File Version HistorySpartan-3A DSP v1.29 Speed Grade Designations At the Output pin. The DCM is not Use TimingPin-to-Pin Clock-to-Output Times for the IOB Output Path Rate, without DCMHold Times Ifddelayvalue =Speed Grade Symbol Description ConditionsDevice Min Units Setup Times Set/Reset Pulse WidthIoplid Differential Standards Single-Ended StandardsLvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI333 PCI663Set/Reset Times Asynchronous Output Enable/Disable TimesTiming for the IOB Three-State Path QuietIO QuietIO 27.67QuietIO 24.97 QuietIO 25.92Inputs Only LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25Inputs Signal Standard Inputs OutputsTiming Measurement Methodology Test Methods for Timing Measurement at I/OsRT Ω DifferentialVicm + Simultaneously Switching Output Guidelines Equivalent VCCO/GND Pairs per BankDevice CS484 FG676 XC3SD1800A XC3SD3400A Signal Standard Top, Bottom Left, Right Package TypeCS484, FG676 Differential Standards Number of I/O Pairs or Channels QuietIO PCI333 PCI663Configurable Logic Block CLB Timing CLB Slicem TimingClock Timing Clock Buffer/Multiplexer Switching Characteristics CLB Shift Register Switching CharacteristicsClock Distribution Switching Characteristics Block RAM Timing Block RAM TimingClock Frequency DSP48A Timing Setup Times for the DSP48ASpeed Grade Symbol Description Setup Times of Data Pins to the Pipeline Register ClockMaximum Frequency Clock to Out from Pipeline Register Clock to Output PinsClock to Out from Input Register Clock to Output Pins Combinatorial Delays from Input Pins to Output PinsRecommended Operating Conditions for the DLL Delay-Locked Loop DLLInput Clock Jitter Tolerance Delay Path Variation4 Digital Clock Manager DCM TimingSpeed Grade Symbol Description Recommended Operating Conditions for the DFS Switching Characteristics for the DFSSpeed Grade Symbol Description Units Min Max Digital Frequency Synthesizer DFSMiscellaneous DCM Timing Phase Shifter PSSwitching Characteristics for the PS in Variable Phase Mode Phase Shifting RangeDnaport Interface Timing DNA Port TimingSymbol Description Min Typ Max Units Suspend Mode TimingEntering Suspend Mode Exiting Suspend Mode Entering Suspend ModeConfiguration and Jtag Timing General Configuration Power-On/Reconfigure TimingAll Speed Grades Symbol Description Device Min Max Units 11.2 Configuration Clock Cclk CharacteristicsMaster Mode Cclk Output Period by ConfigRate Option Setting Cclk clock period byCclk Low and High time Master Mode Cclk Output Minimum Low and High TimeSlave Mode Cclk Input Low and High Time Equivalent Cclk clock frequencyMaster Serial and Slave Serial Mode Timing Slave All Speed Grades Symbol DescriptionMin Max Units Clock-to-Output Times Slave Parallel Mode Timing Symbol Description Minimum Serial Peripheral Interface SPI Configuration TimingSymbol Description Requirement Units Hold time on M20 mode pins after the rising edge of Initb Byte Peripheral Interface BPI Configuration TimingSymbol Description Minimum Maximum Units Setup time on M20 mode pins before the rising edge of InitbParallel NOR Flash Prom chip-select time Symbol Description Requirement UnitsParallel NOR Flash Prom output-enable time Parallel NOR Flash Prom read access timeINTEST, EXTEST, Sample Ieee 1149.1/1553 Jtag Test Access Port TimingDSP48A timing in and Table Diffhstli and Diffhstliii to , , and . Updated Tmds DCDC and Switching Characteristics Types of Pins on Spartan-3A DSP FPGAs Pin TypesType/Color Description Pin Names in Type Code Maximum User I/O by Package Package Pins by TypePinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Power and Ground Supply Pins by PackagePackage Thermal Characteristics Spartan-3A DSP Package Thermal CharacteristicsPinout Descriptions Bank Pin Name CS484 Type Ball CS484 484-Ball Chip-Scale Ball Grid ArrayPinout Table Spartan-3A DSP CS484 PinoutPinout Descriptions Spartan-3A DSP CS484 Pinout AA6 Input VCCO1AA3 Dual AA4AA1 Vref VCCO2 AA5 Vcco AA9VCCO2 VCCO2 VccoVCCO3 Vcco GND AA7GND AB1 Vccaux TMS Jtag TDO Vccaux Progb Config DoneVccaux TCK JtagUser I/Os Per Bank for the XC3SD3400A in the CS484 Package User I/Os by BankFootprint Migration Differences User I/Os Per Bank for the XC3SD1800A in the CS484 PackageLeft Half of Package top view CS484 FootprintRight Half of CS484 Package top view Spartan-3A DSP FG676 Pinout for XC3SD1800A Fpga FG676 676-Ball Fine-Pitch Ball Grid ArrayPinout Table Spartan-3A DSP FG676 Pinout forIOL26N0/GCLK7 IOL26P0/GCLK6IOL31P1/RHCLK2 IOL30N1/RHCLK1IOL30P1/RHCLK0 IOL33P1/RHCLK4IOL27P2/GCLK0 IOL17P2/RDWRBAF7 Input AF3AF4 AF5IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 Vref IP2/VREF2 AB6 VrefAB9 IOL30N2/MOSI/CSIBIOL35N3/LHCLK7 IOL33P3/LHCLK2IOL34N3/LHCLK5 IOL34P3/LHCLK4AD2 AE1 InputAE2 Vref AD1GND AA1 AA6 Vccaux Progb Config TDI Jtag TDOGND AF1 AF6 GND AD3 AD8519 314 User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the FG676 Package Top 128 RightFG676 Package Footprint for XC3SD1800A Fpga top view FG676 FootprintTDO IOL01P0 G20 Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaBank XC3SD3400A Pin Name FG676 Type Ball IOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0IP1/VREF1 VCCO0 Vcco IOL01P1/HDCIOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16 IOL34P1/IRDY1/RHCLK6IOL05N1 AC25 IOL06P1 T25IOL12P2 Y10 VCCO2 AF7 Vcco AE5 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22IOL53P3 IOL53N3 IP3 IOL36N3 IOL37P3IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IP3/VREF3 Vref IOL10N3 IOL03N3 IP3AA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND GND AA1 AA4 AA6 GND AD3 AD5 AD8GND AC5 AC7 GND AB3Vccint AA8 Vccaux AF2 AB4 AB5Bottom 112 Left Vref are on Input pinsUser I/Os Per Bank for the XC3SD3400A in the FG676 Package Top 111 RightPinout Descriptions FG676 Package Footprint for XC3SD3400A Fpga top viewVCCO0 VREF1 VREF1 FG676 Footprint Migration DifferencesPinout Descriptions FG676 Footprint Migration Differences Migration RecommendationsFpga and XC3SD3400A Fpga . Minor edits SPARTAN-3A DSPPinout Descriptions
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