Xilinx DS610 Serial Peripheral Interface SPI Configuration Timing, Symbol Description Minimum

DC and Switching Characteristics

R

Serial Peripheral Interface (SPI) Configuration Timing

PROG_B

(Input)

PUDC_B

(Input)

VS[2:0]

(Input)

M[2:0]

(Input)

INIT_B

(Open-Drain)

PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.

<1:1:1>

Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B goes High. After this point, input values do not matter until DONE goes High, at which

point these pins become user-I/O pins.

<0:0:1>

TMINIT TINITM

New ConfigRate active

	TMCCL1 TMCCH1
	TCCLK1
CCLK
DIN	Data
(Input)
	TCSS

CSO_B

TMCCLn

TCCLK1

TV

Data Data

TDCC

TCCLKn TMCCHn

Data

TCCD

	TCCO
MOSI	Command	Command
	(msb)	(msb-1)
	TDSU	TDH

Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.

Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.

		Shaded values indicate specifications on attached SPI Flash PROM.					DS529-3_06_102506
			Figure 13: Waveforms for Serial Peripheral Interface (SPI) Configuration
Table 51: Timing for Serial Peripheral Interface (SPI) Configuration Mode
	Symbol		Description	Minimum		Maximum	Units
TCCLK1			Initial CCLK clock period		(see Table 45)
TCCLKn			CCLK clock period after FPGA loads ConfigRate setting		(see Table 45)
TMINIT			Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising	50		-	ns
			edge of INIT_B
TINITM			Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising edge	0		-	ns
			of INIT_B
TCCO			Address A[25:0] outputs valid after CCLK falling edge		See Table 49
TDCC			Setup time on D[7:0] data inputs before CCLK falling edge		See Table 49
TCCD			Hold time on D[7:0] data inputs after CCLK falling edge		See Table 49

52 www.xilinx.com DS610-3 (v2.0) July 16, 2007

Product Specification