Mitsubishi DS907x SIP manuals

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Mitsubishi DS907x SIP Manual

Mitsubishi DS907x SIP Manual

174 pages686.43 Kb

TABLE OF CONTENTS
- SECURE MICROCONTROLLER DEVELOPMENT TOOLS
- SECTION 1: INTRODUCTION
- 2
- - SOFTWARE SECURITY
  - SEPARATE ADDRESS/DATA BUS
  - 3LARGE NONVOLATILE MEMORY
  - INSYSTEM LOADING
  - HIGH RELIABILITY OPERATION
  - NOTES:
  - DS2251T 128K Soft Microcontroller Module
  - DS5002FP Secure Microprocessor Chip
- 5
- - DS2252T Secure Microcontroller Module
  - 6SECTION 2: SELECTION GUIDE
  - 7SECTION 3: SECURE MICROCONTROLLER ARCHITECTURE
  - Bus Organization
  - CPU Registers
  - Scratchpad Registers
  - Serial I/O
  - Programmable Timers
  - 8SECURE MICROCONTROLLER ARCHITECTURAL BLOCK DIAGRAM Figure 31
  - 9Parallel I/O
  - Program/Data RAM Interface
  - HighReliability Circuitry
  - Software Encryption Logic
  - Security Lock Logic
  - Vector RAM
  - Timed Access Logic
  - 10Watchdog Timer
  - Resident Loader ROM
  - 11SECTION 4: PROGRAMMERS GUIDE
  - Secure Microcontroller Memory Organization
  - SECURE MICROCONTROLLER MEMORY MAP Figure 41
  - Internal Registers
    - Programmers note
  - 12SCRATCHPAD REGISTER MAP Figure 42
  - 13Program and Data Memory
  - 14DS5000 Series Memory Organization
  - 15DS5000 SERIES MEMORY MAP Figure 43
  - 16DS5000 Memory Map Control
  - DS5000 SERIES MCON REGISTER Figure 44
  - 17DS5001/DS5002 Memory Organization
  - 19PARTITIONABLE MEMORY MAP FOR DS5001/DS5002 SERIES Figure 45
  - 20NONPARTITIONABLE MEMORY MAP FOR DS5001, DS5002 SERIES Figure 46
  - DS5001/DS5002 Memory Mapped Peripherals
  - 21PERIPHERAL ENABLES IN THE DATA MEMORY MAP Figure 47
  - DS5001/DS5002 Memory Map Control
  - 22DS5001/DS5002 SERIES MCON REGISTER Figure 48
  - 23DS5001/DS5002 SERIES RPCTL REGISTER BITS AFFECTING MEMORY Figure 49
  - Loading and Reloading Program Memory
  - 25RELOADING PORTIONS OF A DS5000 SERIES DEVICE Figure 410
  - 27RELOADING A DS5001/DS5002 SERIES DEVICE Figure 411
  - 28Special Function Registers
  - 29DS5000 SERIES SPECIAL FUNCTION REGISTER MAP Figure 412
    - PA3 PA2 PA1 PA0 RA32/8 ECE2
    - SL
    - EWT
    - WTR
  - 30DS5001/DS5002 SERIES SPECIAL FUNCTION REGISTER MAP Figure 413
    - WTR
    - RG0
    - EWT
    - PA3 PA2 PA1 PA0 RG1
    - PM SL
    - MDM CRC
  - 31POWER CONTROL REGISTER Label: PCON Register Address: 087H
  - 33TIMER CONTROL REGISTER Label: TCON Register Address 088H
  - 34TIMER MODE REGISTER Label: TMOD Register Address: 089H
  - 35SERIAL CONTROL REGISTER Label:SCON Register Address: 098H
  - 36INTERRUPT ENABLE REGISTER Label:IE Register Address: 0A8H
  - 37INTERRUPT PRIORITY REGISTER Label:IP Register Address: 0B8H
  - 38DS5001 CRC REGISTER Label: CRC Register Address: 0C1H
  - 39DS5000 MEMORY CONTROL REGISTER Label:MCON Register Address: 0C6H
  - 40DS5001 MCON REGISTER Label: MCON Register Address: 0C6H
  - 42PROGRAM STATUS WORD REGISTER Label:PSW Register Address: 0D0H
  - 43DS5001/DS5002 RPC CONTROL REGISTER Label: RPCTL Register Address: 0D8H
  - 44DS5001/DS5002 RPC STATUS REGISTER Label: RPS Register Address: 0DAH
  - 46INSTRUCTION SET
  - Addressing Modes
  - 48Program Status Flags
  - INSTRUCTIONS THAT AFFECT FLAG SETTINGS
  - 49SECTION 5: MEMORY INTERCONNECT
  - RECOMMENDED SRAMs FOR USE WITH SOFT MICROCONTROLLERS Table 51
  - 50MEMORY INTERCONNECT OF THE DS5000FP Figure 51
  - DS5000 SERIES MODULE BLOCK DIAGRAM Figure 52
  - 51MEMORY INTERCONNECT OF THE PARTITIONABLE DS5001/DS5002 Figure 53
  - 52MEMORY INTERCONNECT OF THE NONPARTITIONABLE DS5001FP, DS5002FP Figure 54
  - 53MEMORY INTERCONNECT USING THE 128K SRAM Figure 55
  - 54DS2251T128 BLOCK DIAGRAM Figure 56
  - 55DS2252T32 BLOCK DIAGRAM Figure 57
  - 56SECTION 6: LITHIUM/BATTERY BACKUP
  - DATA RETENTION
  - BATTERY BACKED CIRCUITS
  - 57POWER SUPPLY SLEW RATE Figure 61
  - BATTERY ATTACH PROCEDURE
  - BATTERY LIFETIME
  - 59LITHIUM BATTERY USAGE
  - FRESHNESS SEAL
  - 60SECTION 7: POWER MANAGEMENT
  - Idle Mode
  - CONTROL/STATUS BITS FOR POWER CONTROL Figure 71
  - 61PIN STATES IN IDLE/STOP MODES Table 71
  - Stop Mode
  - 62Voltage Monitoring Circuitry
  - SECURE MICROCONTROLLER POWER CYCLING TIMING Figure 72
  - 63Power Fail Interrupt
  - Total Power Failure
  - Partial Power Failures
  - 64SECURE MICROCONTROLLER POWER MANAGEMENT Figure 73
  - 65SECTION 8: SOFTWARE CONTROL
  - Timed Access
  - TIMED ACCESS Figure 81
  - 66TIMED ACCESS PROTECTED CONTROL BITS Table 81
  - 67Watchdog Timer
  - 68WATCHDOG TIMER Figure 82
  - 69WATCHDOG TIMER CONTROL BITS
  - CRC MEMORY VERIFICATION
  - 70DS5001 CRC REGISTER (Address 0C1h)
  - 71CRC CODE EXAMPLE Figure 83
  - 72SECTION 9: FIRMWARE SECURITY
  - SECURITY OVERVIEW
  - 73SECURITY LOCK
  - RAM Memory
  - Encrypted Memory
  - 74DS5000 SOFTWARE ENCRYPTION BLOCK DIAGRAM Figure 91
  - DS5002 SOFTWARE ENCRYPTION BLOCK DIAGRAM Figure 92
  - 76Encryption Algorithm
  - Encryption Key
  - Encryption Key Selection and Loading
  - 77Dummy Bus Access
  - DUMMY BUS ACCESS TIMING Figure 93
  - 78Onchip Vector RAM
  - SelfDestruct Input
  - Microprobe/Die Top Coating
  - Random Number Generator
  - 79Security Summary by Part
  - 80APPLICATION: ADVANCED SECURITY TECHNIQUES
  - Avoid Clear Text
  - Avoid CRC or Checksum
  - Avoid Long Straight Runs of Code
  - Use Jumps
  - Use Random values
  - Vector RAM
  - 81Change Code
  - External Circuits
  - Tamper Protection
  - 82SECTION 10: RESET CONDITIONS Reset Sources
  - RESET STATUS BITS Figure 101
  - 83SPECIAL FUNCTION REGISTER RESET STATES Table 101
    - REGISTER LOCATION RESET CONDITION RESET TYPE
  - NOTES:
  - 84Power On Reset
  - POWER ON RESET TIMING Figure 102
  - 85NoVLI Power On Reset
  - External Reset
  - Watchdog Timer Reset
  - 86APPLICATION: RESET ROUTINE EXAMPLE
  - Memory Map
  - 87Interrupts
  - 88Timers
  - Protection
  - 89SECTION 11: INTERRUPTS
  - INTERRUPT SOURCES
  - 90External Interrupts
  - Timer Interrupts
  - Serial Port Interrupts
  - Powerfail Warning Interrupt
  - 91Simulated Interrupts
  - INTERRUPT REQUEST SOURCES Figure 111
  - 92INTERRUPT ENABLE CONTROL BITS Figure 112
  - 93INTERRUPT PRIORITIES
  - INTERRUPT PRIORITY CONTROL BITS Figure 113
  - 94INTERRUPT ACKNOWLEDGE
  - INTERRUPT ACKNOWLEDGE SEQUENCE Figure 114
  - 96SECTION 12: PARALLEL I/O OVERVIEW
  - PORT 0 FUNCTIONAL CIRCUITRY Figure 121
  - 97PORT 1 FUNCTIONAL CIRCUITRY
  - PORT 2 FUNCTIONAL CIRCUITRY
  - 98PORT 3 FUNCTIONAL CIRCUITRY
  - OUTPUT FUNCTIONS
  - 99PARALLEL PORT OUTPUT BUFFERS (PORTS 1, 2, AND 3) Figure 122
  - INPUT FUNCTION
  - 100READMODIFYWRITE INSTRUCTIONS
  - REPROGRAMMABLE PERIPHERAL CONTROLLER (RPC)
  - 101USE OF THE RPC MODE Figure 123
  - USE OF THE RPC MODE Figure 124
  - RPC INTERRUPTS
  - 102RPC STATUS REGISTER STATUS (ADDRESS 0DAH) Figure 125
  - 103RPC PROTOCOL
  - DMA OPERATION
  - 104RPC CONTROL REGISTER RPCTL (ADDRESS 0D8H) Figure 126
  - 105SECTION 13: PROGRAMMABLE TIMERS FUNCTIONAL DESCRIPTION
  - TMOD REGISTER CONTROL BIT SUMMARY Figure 131 Bit Description
  - 106TCON REGISTER CONTROL/STATUS BITS Figure 132
  - 107Mode 0
  - TIMER/COUNTER MODE 0 AND 1 OPERATION Figure 133
  - 108Mode 1
  - Mode 2
  - TIMER/COUNTER MODE 2 OPERATION Figure 134
  - 109Mode 3
  - TIMER 0 MODE 3 OPERATION Figure 135
  - 110SECTION 14: SERIAL I/O FUNCTION DESCRIPTION
  - SERIAL PORT OPERATING MODES Table 141
  - 111SERIAL PORT CONTROL REGISTER Figure 141
  - 112SCON.2: RB8
  - SCON.1: TI
  - SCON.0: RI
  - BAUD RATE GENERATION
  - 113TIMER 1 BAUD RATE GENERATION Table 142
  - SYNCHRONOUS OPERATION (MODE 0)
  - 115MODE 0 BLOCK DIAGRAM AND TIMING Figure 142
    - TRANSMIT TIMING:
    - RECEIVE TIMING:
  - 116ASYNCHRONOUS OPERATION
  - 117Mode 1
  - Mode 2 and 3
  - 118SERIAL PORT MODE 1 BLOCK DIAGRAM Figure 143
  - 119MODE2 AND 3 BLOCK DIAGRAM Figure 144
  - 120APPLICATION: SERIAL PORT INITIALIZATION
  - SERIAL I/O OPERATING MODES
    - 0 1 Mode 1 Asynchronous 10 bits Timer 1 Overflow
  - 124SECTION 15: CPU TIMING OSCILLATOR
  - CRYSTAL CONNECTION Figure 151
  - CLOCK SOURCE INPUT Figure 152
  - 125INSTRUCTION TIMING
  - 126BYTEWIDE RAM INSTRUCTION EXECUTION TIMING Figure 153
  - EXPANDED PROGRAM MEMORY TIMING
  - 127EXPANDED PROGRAM MEMORY FETCH Figure 154
  - 128EXPANDED DATA MEMORY READ Figure 155
  - EXPANDED DATA MEMORY WRITE Figure 156
  - 129EXPANDED DATA MEMORY TIMING
  - 130SECTION 16: PROGRAM LOADING
  - INVOKING THE BOOTSTRAP LOADER
  - 131DS5000 Series
  - DS5001/DS5002 Series
  - EXITING THE LOADER
  - 132INVOKING AND EXITING THE LOADER ON THE DS5001/DS5002 SERIES Figure 161
  - 133SERIAL PROGRAM LOAD MODE
  - SERIAL LOAD CONFIGURATION Figure 162
  - 134AUTOBAUD RATE DETECTION
  - SERIAL LOADER BAUD RATES FOR DIFFERENT CRYSTAL FREQUENCIES Table 161
  - 135BOOTSTRAP LOADER INITIALIZATION
  - COMMAND LINE INTERFACE
  - COMMAND LINE SYNTAX
  - 136COMMAND SUMMARIES ^C
  - C [beginaddress [endaddress]]
  - D [beginaddress [endaddress]]
  - E
  - 137F byte [beginaddress [endaddress]]
  - G
    - byte
    - value
    - values
  - I
  - K byte1 byte2 byte3 byte4 byte5
  - L
  - M
  - N
  - P
  - R
  - T
  - U
  - V
  - W byte
    - byte
  - 138Z
    - VAL
  - ^C
  - Xon/Xoff
  - NOTES ON SELECTED DS5001FP AND DS5002FP COMMANDS
  - 140INTEL HEX FILE FORMAT
  - 141PARALLEL PROGRAM LOAD OPERATION
  - PARALLEL PROGRAM LOAD CONFIGURATION Figure 163
  - PARALLEL PROGRAM LOAD CYCLES Figure 164
  - 142PARALLEL PROGRAM LOAD MODE
  - 8751COMPATIBLE PROGRAM LOAD CYCLES Table 163
  - 143PARALLEL PROGRAMMING CONCERNS
  - RPC PROGRAM MODE OPERATION
  - 144SECTION 17: REALTIME CLOCK
  - DS1215 PHANTOM TIME CHIP
  - DS5000T/DS2250T FUNCTIONAL BLOCK DIAGRAM Figure 171
  - 146PATTERN COMPARISON REGISTER DESCRIPTION Figure 172
    - BYTE 0
  - 147DS1215 REGISTER ENTRY FLOWCHART Figure 173
  - 148DS1215 TIME REGISTERS DESCRIPTION Figure 174
  - REGISTERS
  - SPECIAL BITS
  - 149TIME REGISTER EXAMPLES Figure 175
  - 150DS1283 WATCHDOG TIMEKEEPER CHIP
  - 151DS2251T/DS2252T RTC BLOCK DIAGRAM Figure 176
  - MEMORY MAP
  - 152DS1283 REALTIME CLOCK MEMORY MAP Figure 177
    - TIMEOFDAY ALARM
  - 153DS1283 REALTIME CLOCK COMMAND REGISTER Figure 178
  - 154DS1283 RTC INTERRUPTS
  - ALARM MASKBIT OPERATION Figure 179
  - 155APPLICATION: USING THE DS5000T RTC (DS1215 EXAMPLE)
  - 159APPLICATION: USING THE DS2251T RTC (DS1283 EXAMPLE)
  - 164SECTION 18: TROUBLESHOOTING
  - UNEXPLAINED DEVICE RESETS
  - TIME MICROCONTROLLER READS THE WRONG TIME
  - RAM LOSES DATA WHEN POWERED DOWN
  - 165UNABLE TO INVOKE STOP MODE
  - SERIAL PORT DOES NOT WORK
  - PROGRAM WILL NOT EXECUTE
  - EA is floating
  - Crystal is not running
  - Memory map is not configured
  - No Stack
  - Code is written for an 8052
  - Watchdog is running and unsupported
  - The CRC bit is set on a DS5001
  - 166HIGH CURRENT DRAIN IN STOP MODE
  - DATA IS LOST OR CORRUPTED
  - INT0 IS STUCK LOW ON DS2252T
  - DS5000TK KIT DOES NOT RESPOND TO KIT5K SOFTWARE
  - COMMUNICATION FAILS ON A DS5000TK
  - DEMODS5T PROGRAM DOESNT WORK
  - DOS AND DONTS
  - DONTS RC Resets
  - 167Battery backed signals
  - Negative Voltage Spikes
  - DOS Use Static Protection
  - Use the Loader Port
  - Use the Watchdog
  - Control power supply
  - 168SECTION 19: INSTRUCTION SET DETAILS

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